This article presents an 8-bit time-domain analog-to-digital converter (ADC) that achieves 10 GS/s by aggregating only four time-interleaved channels. It also experiences less than 3.0-dB signal-to-noise and distortion ratio (SNDR) drop at an 18-GHz input frequency from a dc input due to its small input capacitance and inherent voltage-to-time converter (VTC)-based sub-channel buffer. A 16 × time-interpolation-based time-to-digital converter (TDC) resolves in two steps while allowing both the inter-stage gain and the quantization step to be free from calibration over process, supply voltage, and temperature (PVT) variations. Furthermore, through a timing-extended residue transfer scheme, the metastability error rate is suppressed to <10 -8. Fabricated in a 65-nm CMOS process, the prototype ADC achieves a 40.1-dB SNDR for a Nyquist input signal at 10 GS/s while consuming 50.8 mW from a 1.0-V power supply, yielding a Walden figure-of-merit of 61.5 fJ/conversion-step.