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Status | 已發表Published |
An NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28-nm CMOS | |
Xiaofei Ma1,2,3; Yan Lu2,4; Qiang Li1; Wing-Hung Ki5; Rui P. Martins2,4,6 | |
2020-11 | |
Source Publication | IEEE Transactions on Circuits and Systems I: Regular Papers |
ISSN | 1549-8328 |
Volume | 67Issue:11Pages:4041-4052 |
Abstract | This paper presents an NMOS digital low-dropout regulator (LDO) with fast transient response and ultra-low quiescent current, to provide a tunable power supply for near-threshold voltage computing circuits in internet-of-things (IoT) devices. An LDO with an NMOS power transistor can enjoy the intrinsic fast transient response of the source-follower-like power stage, contributing to the proportional (P) part of the control loop. A shift-register-based digital control serves as an excellent candidate for the integral (I) part of the control loop. In addition, we propose a NAND-gate-based high-pass analog path (NAP) as the derivative (D) part of the loop, making the whole control scheme a complete PID control, therefore, achieving a fast transient response. We fabricated two versions of the prototype chip, one with a 35 pF on-chip load capacitor and a fast-transient on-chip load, and the other with no load capacitor, in 28-nm CMOS. The proposed NMOS digital LDO with NAP can handle the load transient of 160 mA/ns with 810-nA quiescent current, achieving 117-mV voltage undershoot. With the proposed techniques, we can achieve nearly two orders of better FoM when comparing it to the state-of-the-art works. |
Keyword | Analog Assisted (Aa) Coarse/fine Tuning Digital Control Digital Low-dropout Regulator (Ldo) Fully Integrated Voltage Regulator (Fivr) Limit Cycle Oscillation (Lco) Nmos Ldo Nonlinear Control Output-capacitor-free |
DOI | 10.1109/TCSI.2020.3009454 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000583739900036 |
Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC445 HOES LANE, PISCATAWAY, NJ 08855-4141 |
Scopus ID | 2-s2.0-85095680555 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | Faculty of Science and Technology THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Corresponding Author | Yan Lu |
Affiliation | 1.Institute of Integrated Circuits and Systems,University of Electronic Science and Technology of China,Chengdu,610054,China 2.State Key Laboratory of Analog and Mixed-Signal,VLSI,University of Macau,Macao 3.Department of Electronic and Computer Engineering,Hong Kong University of Science and Technology,Hong Kong 4.FST-DECE,University of Macau,Macao 5.Department of Electronic and Computer Engineering,Hong Kong University of Science and Technology,Hong Kong 6.Instituto Superior Técnico,Universidade de Lisboa,Lisbon,1049-001,Portugal |
First Author Affilication | University of Macau |
Corresponding Author Affilication | University of Macau; Faculty of Science and Technology |
Recommended Citation GB/T 7714 | Xiaofei Ma,Yan Lu,Qiang Li,et al. An NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(11), 4041-4052. |
APA | Xiaofei Ma., Yan Lu., Qiang Li., Wing-Hung Ki., & Rui P. Martins (2020). An NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28-nm CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(11), 4041-4052. |
MLA | Xiaofei Ma,et al."An NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28-nm CMOS".IEEE Transactions on Circuits and Systems I: Regular Papers 67.11(2020):4041-4052. |
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