| Residential College | false |
| Status | 已發表Published |
| A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS | |
Jiang,Dongyang1; Qi,Liang1; Sin,Sai Weng1  ; Maloberti,Franco2; Martins,R. P.1,3
| |
| 2020-06 | |
| Conference Name | IEEE Symposium on VLSI Circuits |
| Source Publication | IEEE Symposium on VLSI Circuits, Digest of Technical Papers
 |
| Volume | 2020-June |
| Conference Date | 2020/06/16-2020/06/19 |
| Conference Place | Honolulu, HI, USA |
| Abstract | This paper presents a 4X Time-Interleaved (TI) 2-order discrete-time (DT) ΔΣ Modulator (DSM) using digital feedforward extrapolation. Three feedforward paths digitize one channel information first and then extrapolate the other channels fully in the digital domain. Hence, this DSM only needs two opamps in one channel to realize four interleaving paths, thus reducing analog hardware overheads. With the sampling clock @ 520MHz, this 28nm CMOS prototype achieves an equivalent output sampling rate of 2.08GS/s, 208× OSR, 86.1dB SNDR, and 98dB SFDR over a 5MHz BW, while consuming 23.1mW. It results in an FOM of 169.5dB. |
| DOI | 10.1109/VLSICircuits18222.2020.9162798 |
| URL | View the original |
| Indexed By | CPCI-S ; EI |
| Language | 英語English |
| WOS Research Area | Computer Science ; Engineering |
| WOS Subject | Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic |
| WOS ID | WOS:000621657500025 |
| Scopus ID | 2-s2.0-85090204302 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Conference paper |
| Collection | INSTITUTE OF MICROELECTRONICS Faculty of Science and Technology THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
| Corresponding Author | Sin,Sai Weng |
| Affiliation | 1.State-Key Laboratory of Analog and Mixed-Signal Vlsi,Institute of Microelectronics-IME/DECE/FST,University of Macau,Macao 2.University of Pavia,Pavia,Italy 3.Instituto Superior Técnico,Universidade de Lisboa,Portugal |
| First Author Affilication | Faculty of Science and Technology |
| Corresponding Author Affilication | Faculty of Science and Technology |
| Recommended Citation GB/T 7714 | Jiang,Dongyang,Qi,Liang,Sin,Sai Weng,et al. A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS[C], 2020. |
| APA | Jiang,Dongyang., Qi,Liang., Sin,Sai Weng., Maloberti,Franco., & Martins,R. P. (2020). A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS. IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 2020-June. |
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