This article presents a low-dropout regulator (LDO), with analog-proportional (AP) and digital integral (DI) controls. The design concerns are discussed at first, on how to improve the load transient response, enhance the power supply rejection (PSR), and reduce the limit cycle oscillation (LCO). For a good output dc accuracy, the DI section is implemented with shift-register-based coarse- and fine-tuning loops. Meanwhile, the AP section, based on a low-supply flipped-voltage follower (FVF), can respond fast to the load step and input supply ripple. A replica loop is used to define the steady-state output current of AP, allowing a sufficient dynamic swing against the supply ripple. To lower the load current range with no LCO, the AP section will output all the current at very light load. An error amplifier (EA) with moderate gain is added to improve the light-load output accuracy. This EA also improves the PSR by approximately 6 dB. Fabricated in a 65-nm CMOS process, a 65-mV undershoot is measured with a 0-10-mA load current step under 0.6-V supply voltage and 50-mV dropout. Due to the fast AP, a 5-MHz operation clock is applied to the digital section, reducing the overall quiescent current to 29 \mu \text{A}. A 0.37-ps figure of merit (FoM) is then achieved. A -22-dB PSR at 1 MHz is measured at 0.6-V supply, 100-mV dropout, and 10-mA load current.