A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS

doi:10.1109/CICC48029.2020.9075885

UM > THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)

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	A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS
	Zhao,Xiaoteng 1; Chen,Yong1 ; Mak,Pui In1 ; Martins,Rui P.1,2
	2020-04
Conference Name	2020 IEEE Custom Integrated Circuits Conference (CICC)
Source Publication	Proceedings of the Custom Integrated Circuits Conference
Volume	2020-March
Conference Date	22-25 March 2020
Conference Place	Boston
Abstract	A single-loop full-rate bang-bang CDR without the reference and separate frequency detector (FD) is reported. Its phase detector innovates a strobe-point selection scheme and a hybrid control circuit to automate and accelerate the frequency acquisition over a wide frequency range. Prototyped in 28nm CMOS, our CDR achieves a 23-to-29Gb/s capture range of four-level pulse amplitude modulation (PAM-4) data. The acquisition speed [8.2(Gb/s)/μs], die area (0.0285mm) and energy efficiency (0.68pJ/bit) compare favorably with the prior art.
Keyword	Acquisition Speed Alexander Phase Detector (Pd) Bang-bang Bang-bang Clock And Data Recovery (Cdr) Charge Pump (Cp) Frequency Detector (Fd) Full-rate Jitter Tolerance (Jtf) Jitter Transfer Function (Jtf) Single Loop Strobe Point (Sp)
DOI	10.1109/CICC48029.2020.9075885
URL	View the original
Language	英語English
Scopus ID	2-s2.0-85084444667
Fulltext Access	View Full-Text via DOI View Full-Text via Scopus
Citation statistics
Document Type	Conference paper
Collection	THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding Author	Chen,Yong
Affiliation	1.State Key Laboratory of Analog and Mixed-Signal VLSI,IME/FST-ECE,University of Macau,Macao 2.Instituto Superior Técnico,Universidade de Lisboa,Portugal
First Author Affilication	Faculty of Science and Technology
Corresponding Author Affilication	Faculty of Science and Technology
Recommended Citation GB/T 7714	Zhao,Xiaoteng,Chen,Yong,Mak,Pui In,et al. A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS[C], 2020.
APA	Zhao,Xiaoteng., Chen,Yong., Mak,Pui In., & Martins,Rui P. (2020). A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/μs Acquisition Speed of PAM-4 data in 28nm CMOS. Proceedings of the Custom Integrated Circuits Conference, 2020-March.

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