Multi-GS/s ADCs are key blocks for ADC-based serial links and mm-wave 5G receivers. The fastest architecture is the flash ADC [1], but the exponentially growing complexity with resolution makes it energy and area inefficient. Interpolation techniques [2] can reduce the number of comparators but result in lower conversion speeds, while an aggressive interpolation factor in [3] also increases the calibration complexity. SAR ADCs are by far the most power efficient, but only with time interleaving can they reach the required speeds. Hence, pipelined architectures are the preferred choice, but also here clock speeds above 1GS/s are not readily achieved, and the power consumption of the residue amplifier is critical. Previous work [5] explores the option of the fully dynamic pipelined architecture, which only operates up to a relatively low sampling rate of 550MS/s (per channel) owing to its complex residue-transferring realization and calibration. In this work, the pipelined approach is revisited. Different from the conventional architecture that executes 3 serial operations (sampling, quantization and residue amplification) in one clock cycle, a post-amplification residue generation scheme is presented that allows the amplification and conversion to run in parallel. Leveraging a linearized dynamic amplifier and on-chip gain and offset calibration, the prototype achieves 34.2dB SNDR with a Nyquist input at 3.3GS/s. The 6b ADC consumes 5.5mW and 0.0166mm (including calibration), leading to a Walden FoM of 40fJ/conv.-step.