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A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS | |
Fan,Chao1; Yu,Wei Han1; Mak,Pui In1; Martins,Rui P.1,2 | |
2019-12 | |
Source Publication | IEEE Transactions on Circuits and Systems I: Regular Papers |
ISSN | 1549-8328 |
Volume | 66Issue:12Pages:4850-4861 |
Abstract | This paper proposes an SST-CML-Hybrid (SCH) output driver, and its corresponding hybrid-path feed-forward equalization (FFE) scheme, to enhance the energy efficiency of a PAM-4 transmitter (TX). Specifically, the SCH driver features one SST branch + one CML branch to co-synthesize the PAM-4 data, reducing substantially the signaling power, switching power and equalization power. The PAM-4 TX further integrates a half-rate serializer with 4-bit 3-tap FFE, duty-cycle correction circuits and a T-coil output matching network. Prototyped in 28-nm CMOS, the PAM-4 TX achieves a broadband return loss <-10dB up to 50 GHz, and occupies a compact die area of 0.0345 mm. Operating at 40 Gb/s and at a 0.9-V supply, the TX dissipates 19.5 mW, of which 6.4 mW is due to the SCH driver. The corresponding energy efficiencies are 0.16 and 0.5 pJ/bit for the SCH driver and TX, respectively; both compare favorably with the prior art. |
Keyword | Cmos Current-mode-logic (Cml) Driver Feed-forward Equalization (Ffe) Four-level Pulse-amplitude Modulation (Pam-4) Source-series-terminated (Sst) Driver Sst-cml-hybrid (Sch) Driver Transmitter (Tx) |
DOI | 10.1109/TCSI.2019.2936226 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000502344800026 |
Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC445 HOES LANE, PISCATAWAY, NJ 08855-4141 |
Scopus ID | 2-s2.0-85076353559 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING Faculty of Science and Technology THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS |
Corresponding Author | Mak,Pui In |
Affiliation | 1.Department of ECE,State-Key Laboratory of Analog and Mixed-Signal VLSI,Faculty of Science and Technology,University of Macau,Macao 2.Instituto Superior Técnico,Universidade de Lisboa,Lisbon,Portugal |
First Author Affilication | Faculty of Science and Technology |
Corresponding Author Affilication | Faculty of Science and Technology |
Recommended Citation GB/T 7714 | Fan,Chao,Yu,Wei Han,Mak,Pui In,et al. A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(12), 4850-4861. |
APA | Fan,Chao., Yu,Wei Han., Mak,Pui In., & Martins,Rui P. (2019). A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(12), 4850-4861. |
MLA | Fan,Chao,et al."A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS".IEEE Transactions on Circuits and Systems I: Regular Papers 66.12(2019):4850-4861. |
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