Continuous technology scaling has allowed unceasing growth of the sampling rate of a single channel ADC in past decades. Such development not only helps reduce the number of channels in massively time interleaved ADCs, but also contributes to lower their overall jitter and input capacitance, thus enabling a further push on the ADC performance boundary. Being limited by metastability, the conventional SAR architecture is not suitable when both high resolution and speed are essential. While the pipeline SAR offers a higher speed alternative, it also keeps the low and dynamic power nature of the SAR architecture through adopting dynamic or integrating residue amplifiers (RAs) in recent works [1, 2]. With an integrating characteristic, the amplification time can be short but in contrast, the linearity, extra reset time of the load, and PVT sensitivity pose significant design challenges. In this work, rather than adopting the integratingtype amplifier, we present a Gm-R based RA which has a complete-settled amplification characteristic, thus allowing us to compensate the gain variation over temperature easily with a tracking bias technique. Besides this, we use a two-stage amplification to alleviate the RA input parasitic capacitance that enables a small DAC size in all stages. The single channel prototype reaches 1GS/s with 60.02dB SNDR at a Nyquist input consuming 7.6mW from a 1V supply.