Residential College | false |
Status | 已發表Published |
A Fully Integrated LDO with 50-mV Dropout for Power Efficiency Optimization | |
Ma,Xiaofei1,2; Lu,Yan2; Li,Qiang1 | |
2020-04-01 | |
Source Publication | IEEE Transactions on Circuits and Systems II: Express Briefs |
ISSN | 1549-7747 |
Volume | 67Issue:4Pages:725-729 |
Abstract | This brief presents, a fully integrated low-dropout regulator (LDO) with 50-mV dropout voltage for high power efficiency, with a LDO-self-supplied differential error amplifier (EA) for higher power supply rejection (PSR), and a coupled transient enhancement unit for fast transient response. With 50-mV dropout voltage, the LDO can achieve 94.4% power efficiency in the full load condition. The LDO is fabricated in a standard 28-nm bulk CMOS process with 0.0086-mm active area. It features a 288-MHz unity-gain bandwidth (UGB) at 20-mA load current, while consuming a quiescent current of 33 {\mu }\text{A}. With such high bandwidth and the coupled transient enhancement unit, the proposed LDO achieves 270-ps response time for a 0-to-20-mA load transient with 100-ps edge time. The self-supplied EA helps to achieve a PSR of -30 dB even with only 50-mV dropout. The ultra-fast response, small area, and high efficiency features make the proposed LDO very suitable for working as distributed point-of-load regulators in a digital system. |
Keyword | High Power Efficiency Low-dropout Regulator Output-capacitor-free Ultra-fast Response |
DOI | 10.1109/TCSII.2019.2919665 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000522403100025 |
Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 |
Scopus ID | 2-s2.0-85082708090 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | INSTITUTE OF MICROELECTRONICS |
Corresponding Author | Lu,Yan; Li,Qiang |
Affiliation | 1.Integrated Systems Laboratory,University of Electronic Science and Technology of China,Chengdu,China 2.State Key Laboratory of Analog and Mixed-Signal VLSI,University of Macau,Macao |
First Author Affilication | University of Macau |
Corresponding Author Affilication | University of Macau |
Recommended Citation GB/T 7714 | Ma,Xiaofei,Lu,Yan,Li,Qiang. A Fully Integrated LDO with 50-mV Dropout for Power Efficiency Optimization[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2020, 67(4), 725-729. |
APA | Ma,Xiaofei., Lu,Yan., & Li,Qiang (2020). A Fully Integrated LDO with 50-mV Dropout for Power Efficiency Optimization. IEEE Transactions on Circuits and Systems II: Express Briefs, 67(4), 725-729. |
MLA | Ma,Xiaofei,et al."A Fully Integrated LDO with 50-mV Dropout for Power Efficiency Optimization".IEEE Transactions on Circuits and Systems II: Express Briefs 67.4(2020):725-729. |
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