This paper presents a switched-capacitor (SC)bandgap reference (BGR)with second-order curvature compensation for ultra-low power systems. The gate-source voltage of a sub-threshold MOSFET is proposed to implement the second-order curvature compensation voltage in this work. And then, a SC network is used, not only to add the second-order voltage and the first-order one together, but also to fulfill the summing weight effectively and precisely. In this way, the silicon area and power consumption can be reduced simultaneously. Furthermore, the design methodology of summing weight is investigated, and thus the temperature coefficient (TC)can be significantly reduced. The proposed SC-BGR was implemented and simulated in a CMOS 0.18 μm process, the average output voltage is 426.1 mV, achieving a TC of 17.6 ppm/°C from −20 to 100 °C under a 0.5 V minimum supply voltage. With the help of the SC architecture, a small chip area of 0.0975 mm is achieved with only 37.8-nW power consumption.