Two circuit techniques adopted in the design of an embedded programmable-gain amplifier (PGA) for very low-voltage (LV) wireless local-area network systems are presented. A switched-current-resistor (SCR) technique minimizes the bandwidth variation and the transient in gain tuning by stabilizing, concurrently, the PGA’s feedback factor and quiescent-operating point. Another technique, inside-opamp dc-offset canceller (DOC), embeds inside the PGA’s opamp a subthreshold-biased – integrator for extracting its output dc-offset, while negatively feeding the correction (current) signal back to the opamp at an inherent low-impedance node. The resultant main benefits are: 1) the chip area, for realizing the large time constant in dc-offset extraction, is very small and 2) the lower cutoff of the PGA and the DOC-induced nonlinearity and noise are all suppressed by an amount of the loop gain in closed-loop formation. A 1-V three-stage 52-dB gain range PGA reinforcing such two techniques was designed and fabricated in a 3.3-V 0.35- m CMOS process. It consumes 7.4 mW of power while measuring 0 2- s gain-switching transient and +8 4 dBm IIP3. The means of the lower and upper 3-dB cutoffs (averaged over 52-dB gain steps) are 2.25 kHz and 17.1 MHz, respectively.