Residential College | false |
Status | 已發表Published |
An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications | |
Li, Jixuan1; Un, Ka Fai1; Yu, Wei Han1; Mak, Pui In1; Martins, Rui P.2,3 | |
2021-09 | |
Source Publication | IEEE Transactions on Circuits and Systems II: Express Briefs |
ISSN | 1549-7747 |
Volume | 68Issue:9Pages:3143-3147 |
Abstract | The computational efficiency is the prime concern of a computation-intensive deep convolutional neural network (CNN). In this Brief, we report an FPGA-based computation-efficient reconfigurable CNN accelerator. It innovates in the utilization of a kernel partition technique to substantially reduce the repeated access to the input feature maps and the kernels. As a result, it balances the ability for parallel computing while consuming less system power. Experimental results prove that the proposed CNN accelerator achieves a peak throughput of 220.0 GOP/s with an energy efficiency of 22.9 GOPs/W at 151.4 frames/s for the AlexNet. It is also reconfigurable to process VGG-16 befitting complex object recognition. |
Keyword | Computation Efficiency Convolutional Neural Network (Cnn) Fpga Object Recognition Reconfigurability |
DOI | 10.1109/TCSII.2021.3095283 |
URL | View the original |
Indexed By | SCIE ; CPCI-S |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000692209000026 |
Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 |
Scopus ID | 2-s2.0-85114611737 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Corresponding Author | Un, Ka Fai |
Affiliation | 1.State- Key Laboratory of Analog and Mixed-Signal VLSI/IME, DECE, Faculty of Science and Technology, University of Macau, Macao 2.State-Key Laboratory of Analog and Mixed- Signal VLSI/IME, DECE, Faculty of Science and Technology, University of Macau, Macao 3.Instituto Superior Técnico, Universidade de Lisboa, Lisboa, Portugal |
First Author Affilication | Faculty of Science and Technology |
Corresponding Author Affilication | Faculty of Science and Technology |
Recommended Citation GB/T 7714 | Li, Jixuan,Un, Ka Fai,Yu, Wei Han,et al. An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68(9), 3143-3147. |
APA | Li, Jixuan., Un, Ka Fai., Yu, Wei Han., Mak, Pui In., & Martins, Rui P. (2021). An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 68(9), 3143-3147. |
MLA | Li, Jixuan,et al."An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications".IEEE Transactions on Circuits and Systems II: Express Briefs 68.9(2021):3143-3147. |
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