In this article, we present a 2.4-GHz differential class-DE synchronous rectifier. First, we investigate zero-voltage switching (ZVS), zero-current switching (ZCS), and impedance matching requirements for the single-ended class-DE rectifier. Then, we propose a differential topology that achieves near-optimum ZVS, ZCS, and impedance matching with a reduced number of LC networks. We use a coupled inductor structure to reduce the cost overhead of the differential topology and discuss its design considerations. To maintain the ZVS/ZCS operation within a wide input power range, we employ an adaptive bias circuit to adjust the gate bias voltages with the input power. Additionally, we discuss the imperfections caused by load variation. The chip, fabricated in a 65-nm CMOS process, measures the peak power conversion efficiency (PCE) of 68.5% at a 9-dBm input power with a 250-Ω load resistance. The measured input power range when PCE > 40% is 16 dB.