This brief describes a novel Wideband Pre-Distortion (WPD) mechanism as a linearization technique for bandwidth-limited CMOS power amplifiers (PAs). The WPD comprises a common-source amplifier and a hybrid feedback mechanism blended with both active and passive networks to secure a flat gain response from 800 MHz till 3.3 GHz, while maintaining >30% power added efficiency (PAE) at a maximum linear output power of 20 dBm throughout the band of operation. The WPD generates unique gain and phase cancellation mechanisms on-chip therefore alleviating the 3rd-order intermodulation product (IMD3) for an operating bandwidth of 2.5 GHz. Measurement results on 180 nm CMOS, with a supply voltage of 3.3 V indicate that the WPD-PA produces a saturated output power of 24 dBm, in addition to a power gain of 15.5 dB and a peak efficiency of 35.5% at 2.45 GHz. The WPD-PA delivers a maximum linear output power of 20-dBm with an adjacent channel leakage ratio (ACLR) of -30 dBc and error vector magnitude (EVM) of 3.42%, 2.34% and 2.76% at 0.8, 2.45 and 3.3 GHz when measured with the 20-MHz LTE signal. The corresponding maximum linear PAE ranged between 31 to 34%. The chip area is 1.28 mm2.