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| Status | 已發表Published |
| A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS | |
Zhao, Xiaoteng1,2; Chen, Yong1,2  ; Mak, Pui In1,2; Martins, Rui P.1,2,3
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| 2021-09-29 | |
| Source Publication | IEEE JOURNAL OF SOLID-STATE CIRCUITS
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| ISSN | 0018-9200 |
| Volume | 57Issue:2Pages:546-561 |
| Abstract | This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide frequency range. Prototyped in a 28-nm CMOS, the proposed BBCDR occupies a tiny area of 0.0285 mm² and exhibits a 23-to-29-Gb/s capture range. The acquisition speed [8.2 Gb/s/μs] and energy efficiency (0.68 pJ/bit) compare favorably with the state of the art. |
| Keyword | Acquisition Speed Bang-bang Clock And Data Recovery (Bbcdr) Charge Pump (Cp) Clocks Cmos Detectors Four-level Pulse Amplitude Modulation (Pam-4) Frequency Detector (Fd) Frequency Modulation Hybrid Control Circuit (Hcc) Jitter Jitter Tolerance (Jtol) Jitter Transfer Function (Jtf) Logic Gates Phase Detector (Pd) Strobe Point (Sp). Switches Voltage-controlled Oscillators |
| DOI | 10.1109/JSSC.2021.3113773 |
| URL | View the original |
| Indexed By | SCIE |
| Language | 英語English |
| WOS Research Area | Engineering |
| WOS Subject | Engineering, Electrical & Electronic |
| WOS ID | WOS:000732926900001 |
| Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC445 HOES LANE, PISCATAWAY, NJ 08855-4141 |
| Scopus ID | 2-s2.0-85116854849 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Journal article |
| Collection | THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
| Corresponding Author | Chen, Yong |
| Affiliation | 1.University of Macau, State Key Laboratory of Analog and Mixed-Signal VLSI, 999078, Macao 2.Institute of Microelectronic (IME), University of Macau, Department of Electrical and Computer Engineering (DECE), Faculty of Science and Technology, 999078, Macao 3.Instituto Superior Tcnico, Universidade de Lisboa, Lisbon, 1049-001, Portugal |
| First Author Affilication | University of Macau; Faculty of Science and Technology |
| Corresponding Author Affilication | University of Macau; Faculty of Science and Technology |
| Recommended Citation GB/T 7714 | Zhao, Xiaoteng,Chen, Yong,Mak, Pui In,et al. A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 57(2), 546-561. |
| APA | Zhao, Xiaoteng., Chen, Yong., Mak, Pui In., & Martins, Rui P. (2021). A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 57(2), 546-561. |
| MLA | Zhao, Xiaoteng,et al."A 0.0285-mm² 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS".IEEE JOURNAL OF SOLID-STATE CIRCUITS 57.2(2021):546-561. |
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