Residential College | false |
Status | 已發表Published |
An accelerated architecture of change-point detection for FMCW radar mutual interference based on FPGA | |
Yang, Siyuan1; Li, Songyi1; Wu, Jiayan1; Chen, Yong2; Liu, Zhenyu1 | |
2021-08-28 | |
Source Publication | International Journal of Circuit Theory and Applications |
ISSN | 0098-9886 |
Volume | 49Issue:11Pages:3719-3732 |
Abstract | The mutual interference between frequency modulated continuous wave (FMCW) radars seriously affects autonomous driving. The interference will cause a short-duration pulse-like signal, which contains several change points in the time domain. The change-point detection method called bottom-up segmentation (BOTUP) is applied to deal with a short duration pulse-like signal, which has excellent detection accuracy. However, the serial processing of BOTUP will cause considerable delay, which is not conducive to real-time detection of automatic driving. In this paper, an accelerated architecture of BOTUP (ACC-BOTUP) based on field-programmable gate array (FPGA) is proposed. As BOTUP has segmented characteristics and without data dependency between the cost functions, a parallel structure is proposed to reduce the latency. Further, a pipeline structure is proposed to execute the operations of the cost functions in an overlapping manner. Compared with the original BOTUP (O-BOTUP), the latency of ACC-BOTUP is reduced by 82%, which is more suitable for real-time detection in autonomous driving. |
Keyword | Bottom-up Segmentation Change-point Detection Fmcw Radar Fpga Mutual Interference |
DOI | 10.1002/cta.3127 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000690660600001 |
Publisher | WILEY111 RIVER ST, HOBOKEN 07030-5774, NJ |
Scopus ID | 2-s2.0-85113668620 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | INSTITUTE OF MICROELECTRONICS |
Corresponding Author | Liu, Zhenyu |
Affiliation | 1.The School of Information Engineering, Guangdong University of Technology, Guangzhou, China 2.State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macao |
Recommended Citation GB/T 7714 | Yang, Siyuan,Li, Songyi,Wu, Jiayan,et al. An accelerated architecture of change-point detection for FMCW radar mutual interference based on FPGA[J]. International Journal of Circuit Theory and Applications, 2021, 49(11), 3719-3732. |
APA | Yang, Siyuan., Li, Songyi., Wu, Jiayan., Chen, Yong., & Liu, Zhenyu (2021). An accelerated architecture of change-point detection for FMCW radar mutual interference based on FPGA. International Journal of Circuit Theory and Applications, 49(11), 3719-3732. |
MLA | Yang, Siyuan,et al."An accelerated architecture of change-point detection for FMCW radar mutual interference based on FPGA".International Journal of Circuit Theory and Applications 49.11(2021):3719-3732. |
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