The digital low-dropout (D-LDO) regulator can work effectively in low supply voltage. It is appropriate for the digital circuits due to great process scalability. However, D-LDOs suffer a poor transient response caused by the limited sampling clock and the logic delays. Therefore, the transient performance needs to be improved. One of the solutions is getting rid of the control scheme related to synchronous clock. This paper presents an enhanced analog assisted (E-AA) technique for D-LDOs to reduce the voltage spikes. The proposed technique adds a current buffer (CB) and a switch compensated resistor (SCR) into the conventional passive analog assisted loop. The CB is used to amplify the loop gain. The SCR is used to prevent a second droop of output voltage during recovery. The simulation results show that a maximum voltage undershoot is 16.4 mV with a 5 mA/3.8 ns load step and a total capacitor is only 52 pF. Thus, the resulting figure-of-merit (FoM) is 0.41 ps.