The modern SoC chip usually requires multiple clock generators that can achieve low jitter performance over a wide frequency range with the compact area and low power consumption. The multiplying delay-locked-loop (MDLL) employing a ring voltage-controlled oscillator (VCO) is a promising solution to fulfill all these requirements. This chapter focuses on the design of ring-VCO-based MDLL that can achieve low-jitter and spur performance across a wide frequency tuning range in the presence of process-voltage-temperature variations.