16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur

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	16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur
	Yang, Z.; Chen, Y.; Yang, S.; Mak, P. I.; Martins, R. P.
	2019-03-07
Source Publication	FREQUENCY SYNTHESIZERS
Abstract	Recent mm-wave PLLs have explored different architectures to enhance their jitter performance at low power. Without noisy loop components, the injection-locked PLL in [1] using a GHz reference (REF=2.25GHz) can effectively suppress the integrated jitter (86fs rms ), resulting in a better jitter-power FoM (-247.2dB). Yet, high-frequency REF injection leads to large spur (-32dBc), entailing continuous frequency tracking to withstand the PVT variations. Also, at the system level, the GHz REF has to be generated on-chip (i.e. cascaded PLLs). The power overhead, e.g., additional 20mW in [2], and unwanted coupling between the two VCOs become inevitable. To this end, direct-synthesis mm-wave PLLs using a MHz REF are of higher interest, despite the challenge of a large division ratio (N). An example is a Type-II mm-wave PLL reported in [3] that achieves 115fsrms integrated jitter, but the involved divider, charge pump (CP), and VCO totally draw 31mW to suppress the in-band and out-of-band phase noise (PN).
Keyword	iSSPLL
URL	View the original
Language	英語English
The Source to Article	PB_Publication
PUB ID	48653
Document Type	Conference paper
Collection	University of Macau
Corresponding Author	Chen, Y.
Recommended Citation GB/T 7714	Yang, Z.,Chen, Y.,Yang, S.,et al. 16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur[C], 2019.
APA	Yang, Z.., Chen, Y.., Yang, S.., Mak, P. I.., & Martins, R. P. (2019). 16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur. FREQUENCY SYNTHESIZERS.

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