A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter  Exploiting Power-Efficient Cross-Quadrature Clocking  Multiplexers with Maximized Timing Margin

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	A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin
	Chen, Y.; Mak, P. I.; Boon, C.C.; Martins, R. P.
	2018-06-07
Source Publication	IEEE Transactions on Circuits and Systems I: Regular Papers
ISSN	1549-8328
Pages	3014-3026
Abstract	For wireline transmitters delivering a high-speed multi- level signal, such as pulse-amplitude-modulation-4 (PAM4) or duobinary, a high-performance multiplexer (MUX) is critical to serialize the low-speed parallel data into one full-speed output. To enhance the power efficiency and data eye’s opening, this paper proposes a universal 2-to-1 MUX, featuring a cross-quadrature clocking technique to enlarge the timing margin, and a simplified three-latch topology without delay buffers to boost the internal bandwidth (BW). The MUX ratios are extendable to 4-to-2 and 4-to-1, and their benefits are exemplified via a duobinary-signal transmitter. It further includes an output driver unifying the MUX-and-SUM operation, a BW-extended single-to-differential converter (S2D), and an active-inductor-embedded clock buffer for swing enhancement. Also, a predictive method for estimating the duobinary-signal data-dependent jitter (DDJ) according to the load capacitance of the output driver is developed. Fabricated in 65-nm CMOS, the transmitter exhibits a figure-of-merit (FOM) of 1.3 mW/Gb/s at 36 Gb/s, while occupying a compact die area of 0.037 mm 2 .
Keyword	Bandwidth (BW) cross-quadrature clocking data- dependent jitter (DDJ) duobinary multi-level signaling CMOS multiplexer (MUX) figure-of-merit (FOM) timing margin latch D-type flip-flop (DFF) selector
URL	View the original
Language	英語English
The Source to Article	PB_Publication
PUB ID	32773
Document Type	Journal article
Collection	THE STATE KEY LABORATORY OF INTERNET OF THINGS FOR SMART CITY (UNIVERSITY OF MACAU)
Corresponding Author	Chen, Y.
Recommended Citation GB/T 7714	Chen, Y.,Mak, P. I.,Boon, C.C.,et al. A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 3014-3026.
APA	Chen, Y.., Mak, P. I.., Boon, C.C.., & Martins, R. P. (2018). A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin. IEEE Transactions on Circuits and Systems I: Regular Papers, 3014-3026.
MLA	Chen, Y.,et al."A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin".IEEE Transactions on Circuits and Systems I: Regular Papers (2018):3014-3026.

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