| Status | 已發表Published |
| A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration | |
Guo, M. ; Mao, J.; Sin, S. W. ; Wei, H.; Martins, R. P.
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| 2019-04-01 | |
| Source Publication | Proc. of IEEE Custom Integrated Circuits Conference – CICC
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| Abstract | This paper presents a split time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC) with digital background mismatch calibration. Benefitting from the proposed split TI topology, the mismatch calibration convergence speed is fast without any extra analog circuits. A prototype 10-b 1.6-GS/s 7/8- way split TI-SAR ADC in 28-nm CMOS achieves 54.2dB SNDR at Nyquist rate with a 2.5-GHz 3-dB bandwidth, while the power consumption is 12.2mW leading to a Walden FOM of 18.2 fJ per conversion step. |
| Keyword | SAR analog-to-digital converter (ADC) time-interleaved (TI) ADC timing-skew calibration split ADC background mismatch calibration |
| URL | View the original |
| Language | 英語English |
| The Source to Article | PB_Publication |
| PUB ID | 48479 |
| Document Type | Conference paper |
| Collection | University of Macau |
| Corresponding Author | Sin, S. W. |
| Recommended Citation GB/T 7714 | Guo, M.,Mao, J.,Sin, S. W.,et al. A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration[C], 2019. |
| APA | Guo, M.., Mao, J.., Sin, S. W.., Wei, H.., & Martins, R. P. (2019). A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration. Proc. of IEEE Custom Integrated Circuits Conference – CICC. |
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