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Metastability in SAR ADCs
Chan, C. H.; Zhu, Y.; Sin, S. W.; Murmann, B. M.; U, S. P.; Martins, R. P.
2016-04-15
Source PublicationIEEE Transactions on Circuits and Systems II: Express Briefs
ISSN1549-7747
Pages1-5
AbstractThe fundamental limitation of Nyquist ADC architectures towards high speed is metastability. It refers to the inability of a latched comparator to produce a valid decision in a certain available time. This issue is usually severe in high-speed Successive-Approximation-Register (SAR) ADCs due to their serial conversion scheme, which includes the regeneration and the reset process of the comparator in a feedback loop, thus significantly reducing the available time for the regeneration. As the metastability phenomenon has already been explored and analyzed in Flash and Pipeline architectures, a SAR ADC is studied here. Our analysis considers the probability of metastability errors as a function of their magnitude and is customized for a timer-based asynchronous SAR ADC (with loop time-out). The resulting framework can also quantify the metastability in a synchronous architecture and we provide a numerical comparison. To validate the analysis, measurement results of an 8-bit 130 MS/s SAR ADC in 90 nm CMOS are provided.
Keywordanalog-to-digital converter (ADC) metastability SAR comparator
URLView the original
Language英語English
The Source to ArticlePB_Publication
PUB ID20620
Document TypeJournal article
CollectionInstitute of Chinese Medical Sciences
Corresponding AuthorZhu, Y.
Recommended Citation
GB/T 7714
Chan, C. H.,Zhu, Y.,Sin, S. W.,et al. Metastability in SAR ADCs[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2016, 1-5.
APA Chan, C. H.., Zhu, Y.., Sin, S. W.., Murmann, B. M.., U, S. P.., & Martins, R. P. (2016). Metastability in SAR ADCs. IEEE Transactions on Circuits and Systems II: Express Briefs, 1-5.
MLA Chan, C. H.,et al."Metastability in SAR ADCs".IEEE Transactions on Circuits and Systems II: Express Briefs (2016):1-5.
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