| Status | 已發表Published |
| A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on Pipelined-SAR Structure | |
Song, Y.; Zhu, Y.; Chan, C. H. ; Geng , L.; Martins, R. P.
| |
| 2018-06-01 | |
| Source Publication | Proceeding of 2018 IEEE Symposium on VLSI Circuits
 |
| Abstract | This paper presents a wide-band and energy-efficient 0-1 MASH ΣΔ ADC which is realized based on the pipelined-SAR structure. It is composed of a 6b SAR ADC in the 1st-stage and a 5b SAR ADC in the 2nd-stage with alternate loading capacitors (ALC) reused for error feedback that realizes an ideal 1st-order noise shaping and simultaneously maintain a high-speed pipeline operation. Fabricated in 65nm CMOS process, the prototype consumes 4.5mW from a 1.2V supply with 77dB SNDR over 12.5MHz bandwidth, leading to a 171.5dB Schreier FoM. |
| Keyword | ΣΔ ADC Pipelined-SAR ADC |
| Language | 英語English |
| The Source to Article | PB_Publication |
| PUB ID | 38535 |
| Document Type | Conference paper |
| Collection | DEPARTMENT OF HISTORY |
| Corresponding Author | Chan, C. H. |
| Recommended Citation GB/T 7714 | Song, Y.,Zhu, Y.,Chan, C. H.,et al. A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on Pipelined-SAR Structure[C], 2018. |
| APA | Song, Y.., Zhu, Y.., Chan, C. H.., Geng , L.., & Martins, R. P. (2018). A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on Pipelined-SAR Structure. Proceeding of 2018 IEEE Symposium on VLSI Circuits. |
| Files in This Item: | There are no files associated with this item. | |||||
Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.
Edit Comment