A 4μm Diameter SPAD Using Less-doped N-Well Guard Ring in Baseline 65nm CMOS

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	A 4μm Diameter SPAD Using Less-doped N-Well Guard Ring in Baseline 65nm CMOS
	Lu, X.; Law, M. K.; Jiang, Y.; Zhao, X.; Mak, P. I.; Martins, R. P.
	2020-05-01
Source Publication	IEEE Transactions on Electron Devices
ISSN	0018-9383
Pages	2223-2225
Abstract	This brief reports a small size single-photon avalanche diode (SPAD) in baseline 65-nm CMOS suitable for low-cost time-of-flight application with high spatial resolution. By exploiting the less-doped n-well region to surround the vertical p-well/deep-n-well multiplication region, the electric field at the SPAD periphery can be reduced without process modifications while avoiding premature lateral breakdown. Validated using TCAD simulations, the fabricated 4-μm diameter SPAD device exhibits a compact device size with a low dark count (73 cps/μm 2 at 20 °C) and a high fill factor (17.7%) using 65-nm baseline CMOS, while demonstrating competitive performance when compared with the state of the art.
Keyword	Baseline CMOS Premature Lateral Break-Down Single-Photon Avalanche Diode (SPAD) Small Pitch
URL	View the original
Language	英語English
The Source to Article	PB_Publication
PUB ID	51217
Document Type	Journal article
Collection	University of Macau
Corresponding Author	Law, M. K.
Recommended Citation GB/T 7714	Lu, X.,Law, M. K.,Jiang, Y.,et al. A 4μm Diameter SPAD Using Less-doped N-Well Guard Ring in Baseline 65nm CMOS[J]. IEEE Transactions on Electron Devices, 2020, 2223-2225.
APA	Lu, X.., Law, M. K.., Jiang, Y.., Zhao, X.., Mak, P. I.., & Martins, R. P. (2020). A 4μm Diameter SPAD Using Less-doped N-Well Guard Ring in Baseline 65nm CMOS. IEEE Transactions on Electron Devices, 2223-2225.
MLA	Lu, X.,et al."A 4μm Diameter SPAD Using Less-doped N-Well Guard Ring in Baseline 65nm CMOS".IEEE Transactions on Electron Devices (2020):2223-2225.

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