This letter presents a 65-dB SNDR ECG SAR analog-to-digital converter (ADC) that utilizes a VCM-based LSB-first switchingscheme for extraordinary low-power operation under low supply voltage.Unlike conventional VCO-based or OSC-based comparators which beingeither power inefficiency or low speed, the adaptive-latching OSC-basedcomparator is presented. It achieves low power while simultaneouslymaintaining an adequate speed under a low supply voltage through theadaptive latching scheme and asynchronous operations. The switchingscheme incorporating the proposed comparator also facilitates the DACmismatch calibration, where no additional analog hardware is neces-sary for the DAC mismatch detection. After calibration, the worst INLdecreases from 2.6 LSBs to 0.85 LSB. The prototype, fabricated in 65-nmLP CMOS, attains 65.48-dB SNDR at 4 KS/s with an OSR = 4 while con-suming only 8.1 nW at 0.55-V supply and leading to a 173.4-dB SchreierFoM.