A sub-0.25pJ/bit 47.6- to-58.8Gb/s reference-less single-loop PAM-4 bang-bang CDR with a deliberately-current- mismatch frequency acquisition technique in 28nm CMOS

UM > INSTITUTE OF MICROELECTRONICS

Status	已發表Published
	A sub-0.25pJ/bit 47.6- to-58.8Gb/s reference-less single-loop PAM-4 bang-bang CDR with a deliberately-current- mismatch frequency acquisition technique in 28nm CMOS
	Zhao, X.; Chen, Y.; Mak, P. I.; Martins, R. P.
	2021-06-07
Source Publication	Circuit Techniques for High-Speed Transceiver Front-Ends
Abstract	This paper reports a reference-less single-loop bang-bang clock and data recovery (BBCDR) circuit featuring fast and robust frequency acquisition without identifying the frequency error polarity. The key idea is a deliberately-current-mismatch charge-pump pair, which avoids the need of a complex high-speed data path or clock path during frequency acquisition. Prototyped in 28nm CMOS, our BBCDR covers a 47.6-to-58.8Gb/s PAM-4 input automatically. The achieved energy efficiency (≤0.25pJ/bit) and acquisition speed [9.8(Gb/s)/μs] compare favorably with the prior art. Keywords—CMOS, reference less, single loop, half-rate, bang-bang clock and data recovery (BBCDR), frequency detector (FD), charge pump (CP), 4-level pulse amplitude modulation (PAM-4), zero (ZNC), positive (PNC), and negative (NNC) net current.
Keyword	CDR CMOS Reference
URL	View the original
Language	英語English
The Source to Article	PB_Publication
PUB ID	59427
Document Type	Conference paper
Collection	INSTITUTE OF MICROELECTRONICS
Corresponding Author	Chen, Y.
Recommended Citation GB/T 7714	Zhao, X.,Chen, Y.,Mak, P. I.,et al. A sub-0.25pJ/bit 47.6- to-58.8Gb/s reference-less single-loop PAM-4 bang-bang CDR with a deliberately-current- mismatch frequency acquisition technique in 28nm CMOS[C], 2021.
APA	Zhao, X.., Chen, Y.., Mak, P. I.., & Martins, R. P. (2021). A sub-0.25pJ/bit 47.6- to-58.8Gb/s reference-less single-loop PAM-4 bang-bang CDR with a deliberately-current- mismatch frequency acquisition technique in 28nm CMOS. Circuit Techniques for High-Speed Transceiver Front-Ends.

Files in This Item:
There are no files associated with this item.

If you have any objections to this item, please fill out the form below and the administrator will contact you as soon as possible.
Content:
Email：	*
Affiliation No.
Verification Code:	Refresh

Any comments and suggestions are welcomed.
Title:	*
Content:
Email：	*
Verification Code:	Refresh