This brief describes an integer-N-type-II sub-sampling phase-locked loop (SS-PLL) incorporating a push-pull sub-sampling phase detector to significantly suppress the spur-induced binary frequency shift keying modulation (BFSK) effect and a low-power fast-locking frequency-locked loop (FLL) to shorten the settling time. Prototyped in 65-nm CMOS, the SS-PLL at 3.3 GHz shows a reference spur of -82.2 dBc, an integrated jitter of 64.9 fsrms (1 kHz to 40 MHz), and an in-band phase noise (PN) of -128.4 dBc/Hz at 1-MHz offset. The corresponding jitter power figure of merit (FOM) is -255 dB. The entire SS-PLL consumes 7.5 mW, with only 90 μW associated with the FLL.