The data acquisition system is widely used in electronic measuring instruments, for example, the oscilloscope. The development direction of the oscilloscope reflects the research status and development trend of the data acquisition system. Currently, the index of oscilloscopes is progressing toward a high sampling rate, and the performance of the analog-to-digital converter (ADC) has become the main bottleneck to improve the sampling rate of the acquisition system. The alternate sampling technology entails multichannel low sampling rate ADCs to achieve high sampling rate data acquisition through parallel sampling and realize data reconstruction through software. The sampling clock is the most important and difficult part of the system. For ADCs with the 100-GS/s sampling rate and 10-bit resolution, the jitter of the sampling clock needs to be in sub-100 fs along with multiple phases. Based on the principle of injection locking, a 150-GS/s sampling clock is proposed in this paper, which is implemented in a 0.15-μm GaAs process, and the 50-GHz locking range is achieved. The measurement results show that the sampling frequency is 150 GS/s, the root mean square (RMS) jitter is 63 fs with the integrated range from 1 kHz to 10 MHz, and the phase noise can meet the sampling requirements of the 10-bit oscilloscope, which can provide a clocking scheme for small and low-power ultrahigh-speed oscilloscope.