This article presents a second-order successive approximation register (SAR)-assisted noise-shaping (NS) pipeline analog-to-digital converter (ADC) with optimized noise transfer function (NTF) zeros, background inter-stage gain, and offset calibrations. The NS, realized with an error-feedback (EF) structure, takes place in the second stage of the pipeline. A single amplifier, utilized for residue handover, realizes the EF and the optimized zeros. Copies of the EF capacitors allow their rotation role for residue saving, feedback, and sampling operations, thus omitting the extra phase for the EF operation. While further incorporating a coarse SAR ADC and partial interleaving techniques, the prototype can run at high speed with low power and strong in- band noise suppression. A split-over-time architecture with level-shift-based gain calibration is introduced to ensure the robustness of the ADC, whose hardware also facilitates the offset calibration. Besides, the split second-stage ADCs also share a single comparator, thus enabling a mismatch error insensitive split-ADC architecture with a fast convergence speed of 4000 cycles. Fabricated in 28 nm CMOS, the ADC prototype runs at a 260 MHz sampling rate and retains 20 MHz bandwidth (BW) with a signal-to-noise-and-distortion ratio (SNDR) of 79.1 dB under a small over-sampling ratio (OSR) of 6.5. It consumes 3.1 mW power at a 1 V supply and yields a Schreier figure-of-merit (FoMS) of 177.2 dB.