This article presents an arithmetic progression (AP) switched-capacitor (SC) dc-dc converter topology for systematic step-down reconfigurable rational voltage conversion ratio (VCR) generation while exhibiting soft VCR transitions and quasi-symmetric two-phase charge delivery. The proposed AP topology features fixed steady-state voltage in all the flying capacitors ( $C_{{FLY}})$ irrespective of VCR change, essentially eliminating the internal $C_{{FLY}}$ hard-charging loss due to voltage rebalancing, effectively, improving the overall dynamic efficiency. It also achieves optimal steady-state slow-/fast-switching loss. Furthermore, due to the inherent quasi-symmetric output charge ( $Q_{{OUT}})$ delivery property in the two-phase switching operations, the proposed topology alleviates the VCR-dependent imbalanced per-phase $Q_{{OUT}}$ delivery to relax the $C_{{OUT}}$ requirement in a single-branch converter implementation. We propose a cross-coupled bootstrapping driver (XCBD) operated at half of the converter switching frequency ( $f_{{SW}})$ to adaptively control the flying power switches without relying on dual-branch interleaved architecture. Fabricated in 65-nm CMOS, the implemented AP chip prototype achieves a step-down VCR of 5:4/3/2/1 and converts a 1.5-V input to a 0.18-1.19-V output. With a measured steady-state peak power conversion efficiency (PCE) of 93.7%, this work can deliver a maximum output current of 400 mA while attaining an average conversion efficiency of up to 89% under a periodic VCR transition at 100 kHz as benefitted from the intrinsic soft VCR transition and low conduction loss properties.