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A Single-Stage Delay-Tuned Active Rectifier for Constant-Current Constant-Voltage Wireless Charging Conference paper
Xianglong Bai, Fangyu Mao, Yan Lu, Chenchang Zhan, Rui P. Martins. A Single-Stage Delay-Tuned Active Rectifier for Constant-Current Constant-Voltage Wireless Charging[C]:IEEE, 2020, 47-49.
Authors:  Xianglong Bai;  Fangyu Mao;  Yan Lu;  Chenchang Zhan;  Rui P. Martins
Favorite | TC[WOS]:4 TC[Scopus]:4 | Submit date：2021/03/04
Active Rectifier  Constant Current  Constant Voltage  Current Sensing  Li-ion Battery Charging  Single-stage Wireless Charging  
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique Conference paper
Lingshan Kong, Yong Chen, Haohong Yu, Quan Pan, Chirn Chye Boon, Pui-In Mak, Rui P. Martins. Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique[C]:IEEE, 2020, 153-156.
Authors:  Lingshan Kong;  Yong Chen;  Haohong Yu;  Quan Pan;  Chirn Chye Boon; et al.
Favorite | TC[WOS]:4 TC[Scopus]:5 | Submit date：2021/03/09
Variable-gain Amplifier (Vga)  Cmos  Pseudo-current Steering  Wide-tuning Gain Control  Bandwidth (Bw)  High-speed Transceiver  Negative Capacitance  Peak-to-peak Jitter  
A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS Conference paper
Arya Balachandran, Yong Chen, Chirn Chye Boon. A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS[C]:IEEE, 2019, 221-224.
Authors:  Arya Balachandran;  Yong Chen;  Chirn Chye Boon
Favorite | TC[Scopus]:17 | Submit date：2021/10/28
Cmos  Analog Front-end (Afe)  Low Frequency Equalization (Lfeq)  Inductorless  Continuous-time Linear Equalizer (Ctle)  Inductorless  Channel Loss  Decision Feedback Equalization (Dfe)  Receiver  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS Conference paper
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui P. Martins. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS[C]:IEEE, 2019, 229-232.
Authors:  Xiaoteng Zhao;  Yong Chen;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:6 TC[Scopus]:7 | Submit date：2021/03/09
4-/8-level Pulse Amplitude Modulation (Pam-4/8)  Bang-bang Phase Detector (Bbpd)  Clock And Data Recovery (Cdr)  Half Rate  Non-return To Zero (Nrz)  Strongarm Comparator  Voltage-to-current (V/i) Converter  Xor  
Review and Comparison of Integrated Inductive-Based Hybrid Step-Down DC-DC Converter under CCM Operation Conference paper
Chi-Wa U, Wen-Liang Zeng, Chi-Seng Lam. Review and Comparison of Integrated Inductive-Based Hybrid Step-Down DC-DC Converter under CCM Operation[C]:IEEE, 2019, 49-52.
Authors:  Chi-Wa U;  Wen-Liang Zeng;  Chi-Seng Lam
Favorite | TC[WOS]:1 TC[Scopus]:4 | Submit date：2021/03/11
3-level Buck Converter (3lbc)  Conventional Buck Converter (Cbc)  Power Efficiency  Switched-inductor-capacitor Buck Converter (Sicbc)  Voltage Ripple  
A low-dropout regulator with power supply rejection improvement by bandwidth-zero tracking Conference paper
Lu Y., Yao R.H., Huang D.Q., Su J., Jiang J., Ki W.-H.. A low-dropout regulator with power supply rejection improvement by bandwidth-zero tracking[C], 2015, 105-108.
Authors:  Lu Y.;  Yao R.H.;  Huang D.Q.;  Su J.;  Jiang J.; et al.
Favorite | TC[WOS]:3 TC[Scopus]:2 | Submit date：2019/02/14
Analysis of two-phase on-chip step-down switched capacitor power converters Conference paper
Jiang J., Lu Y., Ki W.-H.. Analysis of two-phase on-chip step-down switched capacitor power converters[C], 2015, 575-578.
Authors:  Jiang J.;  Lu Y.;  Ki W.-H.
Favorite | TC[WOS]:2 TC[Scopus]:3 | Submit date：2019/02/14
A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators Conference paper
Jiang Y., Wong K.-F., Cai C.-Y., Sin S.-W., U S.-P., Martins R.P.. A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators[C], 2011, 1011-1014.
Authors:  Jiang Y.;  Wong K.-F.;  Cai C.-Y.;  Sin S.-W.;  U S.-P.; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2 | Submit date：2019/02/11
Clock-jitter Sensitivity  Continuous-time  Sigma-delta Modulator  Switched Current Dac  
An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs Conference paper
Li D., Sin S.-W., Seng-Pan U., Martins R.P.. An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs[C], 2010, 208-211.
Authors:  Li D.;  Sin S.-W.;  Seng-Pan U.;  Martins R.P.
Favorite | TC[WOS]:2 TC[Scopus]:3 | Submit date：2019/02/11
Capacitor Mismatch  Digital Calibration  Interstage Gain Error  Pipelined Adcs  
Multi-spurious suppression for microstrip dual-mode bandpass filter using triple U-shaped defected ground structure Conference paper
Chon Chio Leong, Sio Weng Ting, Kam Weng Tam. Multi-spurious suppression for microstrip dual-mode bandpass filter using triple U-shaped defected ground structure[C], 2009, 90-92.
Authors:  Chon Chio Leong;  Sio Weng Ting;  Kam Weng Tam
Favorite | TC[WOS]:1 TC[Scopus]:2 | Submit date：2019/02/13
Defected Ground Structure  Dual-mode Bandpass Filter  Harmonic Suppression  Multi-bandgaps  U-shaped