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A Battery-Input Sub-1V Output 92.9% Peak Efficiency 0.3 A/mm 2 Current Density Hybrid SC-Parallel-Inductor Buck Converter with Reduced Inductor Current in 65nm CMOS Conference paper
Guigang Cai, Yan Lu, Rui Martins. A Battery-Input Sub-1V Output 92.9% Peak Efficiency 0.3 A/mm 2 Current Density Hybrid SC-Parallel-Inductor Buck Converter with Reduced Inductor Current in 65nm CMOS[C], 2022.
Authors:  Guigang Cai;  Yan Lu;  Rui Martins
Favorite |  | Submit date：2022/08/31
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
Zheng, Z., Wei, W., Lagos, J., Martens, E., Zhu, Y., Chan, C. H., Craninckx, J., Martins, R. P.. 16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation[C], 2020.
Authors:  Zheng, Z.;  Wei, W.;  Lagos, J.;  Martens, E.;  Zhu, Y.; et al.
Favorite |  | Submit date：2022/01/25
Amplifiers  Analogue-digital Conversion  Calibration  Interpolation  Dynamic Pipelined Adc  Dynamic Pipelined Architecture  Linearized Dynamic Amplifier  Post-amplification Residue Generation Scheme  Residue Amplification  Complex Residue-transferring Realization  Residue Amplifier  Power Consumption  Sar Adc  Calibration Complexity  Aggressive Interpolation Factor  Flash Adc  Mm-wave 5g Receivers  Adc-based Serial Links  Power 5.5 Mw  Calibration  Quantization (Signal)  Clocks  System-on-chip  Interpolation  Prototype  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS Conference paper
Jun Yin, Shiheng Yang, Haidong Yi, Wei-Han Yu, Pui-In Mak, Rui P. Martins. A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS[C]. Institute of Electrical and Electronics Engineers Inc., 2019, 450-452.
Authors:  Jun Yin;  Shiheng Yang;  Haidong Yi;  Wei-Han Yu;  Pui-In Mak; et al.
Favorite | TC[WOS]:18 TC[Scopus]:19 | Submit date：2018/11/06
27.3 A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement Conference paper
Chen, Zhiyuan, Jiang, Yang, Law, Man-Kay, Mak, Pui-In, Zeng, Xiaoyang, Martins, Rui P.. 27.3 A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement[C], 2019.
Authors:  Chen, Zhiyuan;  Jiang, Yang;  Law, Man-Kay;  Mak, Pui-In;  Zeng, Xiaoyang; et al.
Favorite | TC[Scopus]:28 | Submit date：2019/03/13
A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement Conference paper
Chen, Z., Jiang, Y., Law, M. K., Mak, P. I., Zeng, X., Martins, R. P.. A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement[C], 2019.
Authors:  Chen, Z.;  Jiang, Y.;  Law, M. K.;  Mak, P. I.;  Zeng, X.; et al.
Favorite |  | Submit date：2022/01/24
Piezoelectric Energy-Harvesting Interface  Split-Phase Flipping-Capacitor Rectifier (SPFCR)  Capacitor Reuse  Multiple-VCR SC DC-DC Converter  
A −246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT Conference paper
Yang, X., Chan, C. H., Zhu, Y., Martins, R. P.. A −246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT[C], 2019.
Authors:  Yang, X.;  Chan, C. H.;  Zhu, Y.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
Phase locked loops  Jitter  Clocks  Phase noise  Wideband  Frequency locked loops  
A 0.22-to-2.4V-input fine-grained fully integrated rational buck-boost SC DC-DC converter using algorithmic voltage-feed-in (AVFI) topology achieving 84.1% peak efficiency at 13.2mW/mm2 Conference paper
Jiang, Yang, Law, Man-Kay, Mak, Pui-In, Martins, Rui P.. A 0.22-to-2.4V-input fine-grained fully integrated rational buck-boost SC DC-DC converter using algorithmic voltage-feed-in (AVFI) topology achieving 84.1% peak efficiency at 13.2mW/mm2[C]. Institute of Electrical and Electronics Engineers Inc., 2018, 422-424.
Authors:  Jiang, Yang;  Law, Man-Kay;  Mak, Pui-In;  Martins, Rui P.
Favorite | TC[WOS]:19 TC[Scopus]:22 | Submit date：2018/11/06
A 0.4V 430nA Quiescent Current NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28nm CMOS Conference paper
Xiaofei Ma, Yan Lu, Rui P. Martins, Qiang Li. A 0.4V 430nA Quiescent Current NMOS Digital LDO with NAND-Based Analog-Assisted Loop in 28nm CMOS[C]. Institute of Electrical and Electronics Engineers Inc., 2018, 306-308.
Authors:  Xiaofei Ma;  Yan Lu;  Rui P. Martins;  Qiang Li
Favorite | TC[WOS]:52 TC[Scopus]:59 | Submit date：2018/11/06
An inverse-class-F CMOS VCO with intrinsic-high-Q 1st- and 2nd-harmonic resonances for 1/f2-to-1/f3 phase-noise suppression achieving 196.2dBc/Hz FOM Conference paper
Chee-Cheow Lim, Jun Yin, Pui-In Mak, Harikrishnan Ramiah, Rui P. Martins. An inverse-class-F CMOS VCO with intrinsic-high-Q 1st- and 2nd-harmonic resonances for 1/f2-to-1/f3 phase-noise suppression achieving 196.2dBc/Hz FOM[C], 2018, 374-376.
Authors:  Chee-Cheow Lim;  Jun Yin;  Pui-In Mak;  Harikrishnan Ramiah;  Rui P. Martins
Favorite | TC[WOS]:28 TC[Scopus]:28 | Submit date：2019/02/11