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A Reconfigurable Floating-Point Compute-In-Memory With Analog Exponent Pre-Processes Journal article
He, Pengyu, Zhao, Yuanzhe, Xie, Heng, Wang, Yang, Yin, Shouyi, Li, Li, Zhu, Yan, Martins, Rui P., Chan, Chi Hang, Zhang, Minglei. A Reconfigurable Floating-Point Compute-In-Memory With Analog Exponent Pre-Processes[J]. IEEE Solid-State Circuits Letters, 2024, 7, 271-274.
Authors:  He, Pengyu;  Zhao, Yuanzhe;  Xie, Heng;  Wang, Yang;  Yin, Shouyi; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/10/10
Compute-in-memory Macro(Cim)  Exponent Pre-process  Floating-point(Fp)  Reconfigurable  Segmented Computation  
Editorial Welcome to the New Editor-in-Chief Other
2024-01-01
Authors:  Carusone, Tony Chan;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2024/05/16
A Swing-Enhanced Class-D VCO Using a Periodically Time-Varying (PTV) Inductor Journal article
Lin, Xiaoqi, Yin, Jun, Mak, Pui In, Martins, Rui P.. A Swing-Enhanced Class-D VCO Using a Periodically Time-Varying (PTV) Inductor[J]. IEEE Solid-State Circuits Letters, 2022, 5, 25-28.
Authors:  Lin, Xiaoqi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:5 TC[Scopus]:5 | Submit date：2022/05/17
Inductors  Voltage-controlled Oscillators  Voltage  Capacitors  Resonant Frequency  Transistors  Transformers  
A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM Journal article
Yang,Zunsong, Chen,Yong, Mak,Pui In, Martins,Rui P.. A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with -78.7-dBc REF Spur, -128.1-dBc/Hz Absolute In-Band PN and -254-dB FOM[J]. IEEE Solid-State Circuits Letters, 2020, 3, 494-497.
Authors:  Yang,Zunsong;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:18 TC[Scopus]:19 | Submit date：2021/03/09
Cmos  In-band Phase Noise (Pn)  Narrow-pulse-sampling (Nps)  Phase-locked Loop (Pll)  Reference (Ref) Spur  T-shape Switch  Type-i  Voltage-controlled Oscillator (Vco)  
A Two-Phase Three-Level Buck DC–DC Converter With X-Connected Flying Capacitors for Current Balancing Journal article
Wang,Chuang, Lu,Yan, Huang, Mo, Martins,Rui P.. A Two-Phase Three-Level Buck DC–DC Converter With X-Connected Flying Capacitors for Current Balancing[J]. IEEE Solid-State Circuits Letters, 2020, 3, 442-445.
Authors:  Wang,Chuang;  Lu,Yan;  Huang, Mo;  Martins,Rui P.
Favorite | TC[WOS]:11 TC[Scopus]:18 | Submit date：2022/01/25
Buck Converter  Cross-connected  Current Balancing  Dc-dc Converter  Two-phase Three-level Converter  
A Two-Phase Three-Level Buck DC-DC Converter with X-Connected Flying Capacitors for Current Balancing Journal article
Wang,Chuang, Lu,Yan, Huang, Mo, Martins,Rui P.. A Two-Phase Three-Level Buck DC-DC Converter with X-Connected Flying Capacitors for Current Balancing[J]. IEEE Solid-State Circuits Letters, 2020, 3, 442-445.
Authors:  Wang,Chuang;  Lu,Yan;  Huang, Mo;  Martins,Rui P.
Favorite | TC[WOS]:11 TC[Scopus]:18 | Submit date：2021/03/09
Buck Converter  Cross-connected  Current Balancing  Dc-dc Converter  Two-phase Three-level Converter  
A 65.5-dB SNDR 8.1-11.1-nW ECG SAR ADC with Adaptive-Latching OSC-Based Comparator and DAC Calibration Journal article
Li,Kejin, Zhang,Wai Hong, Chen,Yun, Zhu,Yan, Chan,Chi Hang, Martins,Rui Paulo. A 65.5-dB SNDR 8.1-11.1-nW ECG SAR ADC with Adaptive-Latching OSC-Based Comparator and DAC Calibration[J]. IEEE Solid-State Circuits Letters, 2020, 3, 482-485.
Authors:  Li,Kejin;  Zhang,Wai Hong;  Chen,Yun;  Zhu,Yan;  Chan,Chi Hang; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4 | Submit date：2021/03/09
Calibration  Ecg Analog-to-digital Converter (Adc)  Lsb-first Algorithm  Osc-based Comparator  
A 6.5x7 µm2 0.98-to-1.5 mW Non-Self-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4 to 44 GHz) Journal article
Chen, Y., Yang, Z., Zhao, X., Huang, Y., Mak, P. I., Martins, R. P.. A 6.5x7 µm2 0.98-to-1.5 mW Non-Self-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4 to 44 GHz)[J]. IEEE SOLID-STATE CIRCUITS LETTERS, 2019, 37-40.
Authors:  Chen, Y.;  Yang, Z.;  Zhao, X.;  Huang, Y.;  Mak, P. I.; et al.
Favorite |  | Submit date：2022/01/25
Frequency divider  locking range (LR)  5G radio band  self-oscillationmode (SOM)  phase noise  non-self-oscillation-mode (NSOM)  
A 6.5 ×7μ m2 0.98-to-1.5 mW Nonself-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4-44 GHz) Journal article
Chen,Yong, Yang,Zunsong, Zhao,Xiaoteng, Huang,Yunbo, Mak,Pui In, Martins,Rui P.. A 6.5 ×7μ m2 0.98-to-1.5 mW Nonself-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4-44 GHz)[J]. IEEE Solid-State Circuits Letters, 2019, 2(5), 37-40.
Authors:  Chen,Yong;  Yang,Zunsong;  Zhao,Xiaoteng;  Huang,Yunbo;  Mak,Pui In; et al.
Favorite | TC[WOS]:19 TC[Scopus]:23 | Submit date：2021/03/09
5g Bands  Current-mode-logic (Cml)  Figure-of-merit (Fom)  Frequency Divider  Locking Range (Lr)  Non-self-oscillation-mode (Nsom)  Phasor  Self-oscillation-mode (Som)  
A digital LDO with Co-SA logics and TSPC dynamic latches for fast transient response Journal article
Zhao,Lei, Lu,Yan, Martins,Rui P.. A digital LDO with Co-SA logics and TSPC dynamic latches for fast transient response[J]. IEEE Solid-State Circuits Letters, 2018, 1(6), 154-157.
Authors:  Zhao,Lei;  Lu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:16  IF:2.2/2.0 | Submit date：2021/03/09
Continuous-time Comparator  Digital Low-dropout Regulator (Dldo)  Dynamic Logic  Transient Response  True Single-phase Clock (Tspc) Latch