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An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications Journal article
Cao, Rujian, Zhao, Zhongyu, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II-Express Briefs, 2024, 71(11), 4688-4692.
Authors:  Cao, Rujian;  Zhao, Zhongyu;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/10/10
Sparse Matrices  Computational Modeling  Transformers  Hardware  Energy Efficiency  Circuits  Throughput  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Sparsity  Transformer  
A 512-nW 0.003-mm2 Forward-Forward Black Box Trainer for an Analog Voice Activity Detector in 28-nm CMOS Journal article
LI JUNDE, XIN GUOQIANG, YU WEI HAN, UN KA FAI, RUI P MARTINS, MAK PUI IN. A 512-nW 0.003-mm2 Forward-Forward Black Box Trainer for an Analog Voice Activity Detector in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2024, 71(11), 4703-4707.
Authors:  LI JUNDE;  XIN GUOQIANG;  YU WEI HAN;  UN KA FAI;  RUI P MARTINS; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/08/29
Voice Activity Detection  Convolution Neural Network  Edge Learning  Forward-forward Algorithm  Black Box Training  Back Propagation  
A Complementary Drain-Grounded VCO-PA Improving Transmit Efficiency Over a Wide EIRP Range Journal article
Yang, Zhizhan, Yin, Jun, Martins, Rui P., Mak, Pui In. A Complementary Drain-Grounded VCO-PA Improving Transmit Efficiency Over a Wide EIRP Range[J]. IEEE Transactions on Circuits and Systems II-Express Briefs, 2024, 71(10), 4422-4426.
Authors:  Yang, Zhizhan;  Yin, Jun;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/06/05
Voltage-controlled Oscillator  Power Amplifier  Transmitter Power Efficiency  Energy Harvesting  Ultra-low Power Transmitter  Loop Antenna  
Proportional-Derivative Control of Discrete-Time Positive Systems: A State-Space Approach Journal article
Liu, Jason J. R., Yang, Nachuan, Kwok, Ka-Wai, Lam, James. Proportional-Derivative Control of Discrete-Time Positive Systems: A State-Space Approach[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2024, 71(10), 4491-4495.
Authors:  Liu, Jason J. R.;  Yang, Nachuan;  Kwok, Ka-Wai;  Lam, James
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:4.0/3.7 | Submit date：2023/06/19
Discrete-time Systems  Pd Control  Positive System  
An FPGA-Based Transformer Accelerator with Parallel Unstructured Sparsity Handling for Question-Answering Applications Journal article
CAO RUJIAN, ZHAO ZHONGYU, UN KA FAI, YU WEI HAN, RUI P. MARTINS, MAK PUI IN. An FPGA-Based Transformer Accelerator with Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024.
Authors:  CAO RUJIAN;  ZHAO ZHONGYU;  UN KA FAI;  YU WEI HAN;  RUI P. MARTINS; et al.
Favorite |  | Submit date：2024/08/29
Mode-Holding Control for Markov Jump Systems: When Event-Triggering Effect Meets DoS Attack Threat Journal article
Cao, Zhiru, Liu, Jason J.R., Peng, Chen. Mode-Holding Control for Markov Jump Systems: When Event-Triggering Effect Meets DoS Attack Threat[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(6), 3096-3100.
Authors:  Cao, Zhiru;  Liu, Jason J.R.;  Peng, Chen
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.0/3.7 | Submit date：2024/05/16
Markov Jump System  Networked Control System  Adaptive Event-triggered Mechanism  Stochastic Dos Attack  Sliding Mode Control  
A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control Journal article
Yu, Kai, Yang, Shangru, Li, Sizhen, Huang, Mo. A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(4), 1754-1758.
Authors:  Yu, Kai;  Yang, Shangru;  Li, Sizhen;  Huang, Mo
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:4.0/3.7 | Submit date：2024/05/02
Cmos Voltage Reference  Dibl Effect Compensation  Line Sensitivity  Power Supply Rejection Ratio  Self-biased  Ultra-low Power  
A 12V-to-1V Outphase-Interleaved SC Hybrid Converter With Enhanced Inductor De-Energizing Slew Rate and Adaptive Deadtime Control Journal article
Zhang, Xiongjie, Li, Xinman, Zhao, Anyang, Jiang, Yang, Zhang, Weihang, Zhang, Jincheng, Martins, Rui P., Mak, Pui In. A 12V-to-1V Outphase-Interleaved SC Hybrid Converter With Enhanced Inductor De-Energizing Slew Rate and Adaptive Deadtime Control[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(5), 2579-2583.
Authors:  Zhang, Xiongjie;  Li, Xinman;  Zhao, Anyang;  Jiang, Yang;  Zhang, Weihang; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2024/05/16
Adaptive Dead Time  Dc-dc  Fast Load Transient  Hybrid Converter  Inductor Current Reduction  Switched-capacitor  
A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing Journal article
Yaozhong Ou, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu. A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024.
Authors:  Yaozhong Ou;  Wei-Han Yu;  Ka-Fai Un;  Chi-Hang Chan;  Yan Zhu
Favorite |   IF:4.0/3.7 | Submit date：2024/08/07
A 0.011%/V LS and −76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror Journal article
Yu, Kai, Chen, Jiyang, Li, Sizhen, Huang, Mo. A 0.011%/V LS and −76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(3), 1052-1056.
Authors:  Yu, Kai;  Chen, Jiyang;  Li, Sizhen;  Huang, Mo
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/02/22
Cmos Voltage Reference  Line Sensitivity  Power Supply Rejection Ratio  Quasi Self-cascode Current Mirror  Self-biased