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A Two-phase Multi-bit Incremental ADC with Variable Loop Order Journal article
Chen,Kaiquan, Wang,Biao, Liu,Yan, Ye,Fan, Sin,Sai Weng, Wang,Guoxing, Lian,Yong, Qi,Liang. A Two-phase Multi-bit Incremental ADC with Variable Loop Order[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(8), 2724-2728.
Authors:  Chen,Kaiquan;  Wang,Biao;  Liu,Yan;  Ye,Fan;  Sin,Sai Weng; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2023/08/03
Circuits And Systems  Variable Loop Order  Multi-bit Quantizer  Dwa Effectiveness  Noise Penalty  
A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling Conference paper
Wang, Qingxun, Pan, Yuhan, Chen, Kaiquan, Lin, Yu, Wang, Biao, Qi, Liang. A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling[C]:IEEE345 E 47TH ST, NEW YORK, NY 10017 USA, 2023.
Authors:  Wang, Qingxun;  Pan, Yuhan;  Chen, Kaiquan;  Lin, Yu;  Wang, Biao; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2024/02/23
Incremental Analog-to-digital Converter (Iadc)  Linear-exponential  Second-order Noise Coupling (Nc)  The Effective Data Weighting Averaging (Dwa) And Suppression Of Thermal Noise