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A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS Journal article
Li, Manxin, Yao, Yuting, Hu, Biao, Wei, Jipeng, Chen, Yong, Ma, Shunli, Ye, Fan, Ren, Junyan. A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS[J]. IEEE Access, 2021, 9, 77545-77554.
Authors:  Li, Manxin;  Yao, Yuting;  Hu, Biao;  Wei, Jipeng;  Chen, Yong; et al.
Favorite | TC[WOS]:12 TC[Scopus]:16  IF:3.4/3.7 | Submit date：2021/10/28
Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Cmos  Splitcdac  Customized Unit Capacitor  Asynchronous Logic  Figure-of-merit (Fom)