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A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS Journal article
Wang, X. Shawn, Jin, Xin, Du, Jieqiong, Li, Yilei, Du, Yuan, Wong, Chien-Heng, Kuan, Yen-Cheng, Chan, Chi-Hang, Chang, Mau-Chung Frank. A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65(11), 1534-1538.
Authors:  Wang, X. Shawn;  Jin, Xin;  Du, Jieqiong;  Li, Yilei;  Du, Yuan; et al.
Favorite | TC[WOS]:4 TC[Scopus]:6  IF:4.0/3.7 | Submit date：2019/01/17
Analog-to-digital Converter (Adc)  Virtual-ground Sampling  Sar  Time-interleaved