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A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering
Journal article
Li, Ke, Gong, Haoyu, Xianyu, Congzhou, Li, Zhensheng, Qi, Liang, Guo, Mingqiang, Martins, Rui P., Sin, Sai Weng. A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering[J]. IEEE Journal of Solid-State Circuits, 2024.
Authors:
Li, Ke
;
Gong, Haoyu
;
Xianyu, Congzhou
;
Li, Zhensheng
;
Qi, Liang
; et al.
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IF:
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5.6
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Submit date：2025/01/13
Analog-to-digital Converter (Adc)
Cascade Of Integrators With Feedforward (Ciff)
Continuous Time (Ct)
Ct Pipeline (Ctp)
Excess Loop Delay (Eld)
Low-pass Filter (Lpf)
Multistage Noise-shaping (Mash)
Offset Calibration
Signal Transfer Function (Stf) Peaking
