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2020 [1]
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英語English [1]
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IEEE Journal of ... [1]
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A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration
Journal article
Guo, M., Mao, J., Sin,SS. W., Wei, H., Martins, R. P.. A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration[J]. IEEE Journal of Solid-State Circuits, 2020, 693-705.
Authors:
Guo, M.
;
Mao, J.
;
Sin,SS. W.
;
Wei, H.
;
Martins, R. P.
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Submit date：2022/01/25
Calibration
Timing
Clocks
Impedance
Signal To Noise Ratio
Channel Estimation
Jitter
