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Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal–oxide–semiconductor Journal article
Yang, Chaowei, Chen, Yong, Cheng, Kai, Stefano, Crovetti Paolo, Martins, Rui P., Mak, Pui In. Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal–oxide–semiconductor[J]. International Journal of Circuit Theory and Applications, 2024.
Authors:  Yang, Chaowei;  Chen, Yong;  Cheng, Kai;  Stefano, Crovetti Paolo;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.8/1.7 | Submit date：2024/08/05
Clock And Data Recovery (Cdr)  Cmos Figure-of-merit (Fom)  Figure-of-merit With Tuning And Area (Fomta)  Figure-of-merit With Tuning Range (Fomt)  Flicker (1/f)  Noise Noise Transfer Phase Noise (Pn)  Phase-locked Loop (Pll)  Quality Factor Switched-capacitor Array (Sca)  Thermal Noise Transformer Tuning Range (Tr)  Ultra-wide-tuning-range Voltage-controlled Oscillator (Vco)  
A 0.012-mm2 0.244-pJ/bit successive approximation register analog-to-digital converter-based true random number generator for Internet of Things applications in a 65-nm complementary metal–oxide–semiconductor Journal article
Cheng, Kai, Chen, Yong, Stefano, Crovetti Paolo, Martins, Rui P., Mak, Pui In. A 0.012-mm2 0.244-pJ/bit successive approximation register analog-to-digital converter-based true random number generator for Internet of Things applications in a 65-nm complementary metal–oxide–semiconductor[J]. International Journal of Circuit Theory and Applications, 2024.
Authors:  Cheng, Kai;  Chen, Yong;  Stefano, Crovetti Paolo;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.8/1.7 | Submit date：2024/06/05
Analog-to-digital Converter (Adc)  Capacitive Digital-to-analog Converters (Cdacs)  Cryptography  Entropy  National Institute Of StAndards And Technology (Nist)  Successive Approximation Register (Sar)  Thermal Noise  True Random Number Generator (Trng)  
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation Journal article
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhou, Xionghui, Han, Mei, Stefano, Crovetti Paolo, Mak, Pui In, Martins, Rui P.. A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation[J]. International Journal of Circuit Theory and Applications, 2023, 51(5), 1988-2015.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhou, Xionghui;  Han, Mei; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:1.8/1.7 | Submit date：2023/06/05
Bang-bang Clock And Data Recovery (Bbcdr)  Current Mismatch  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Phase Interpolator (Pi)  R-2r Digital-to-analog Converter (Dac)  Ring Oscillator (Ro)  Switched-capacitor (Sc) Array  Wide Capture Range