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Modeling Attack Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability Journal article
Xu, Chongyao, Zhang, Litao, Law, Man Kay, Zhao, Xiaojin, Mak, Pui In, Martins, Rui P.. Modeling Attack Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability[J]. IEEE Internet of Things Journal, 2023, 10(18), 16300 - 16315.
Authors:  Xu, Chongyao;  Zhang, Litao;  Law, Man Kay;  Zhao, Xiaojin;  Mak, Pui In; et al.
Favorite | TC[WOS]:10 TC[Scopus]:15  IF:8.2/9.0 | Submit date：2023/08/03
Field-programmable Gate Array (Fpga)  Machine Learning (Ml) Modeling Attack  Obfuscated Interconnection (Oi)  Physical Unclonable Function (Puf)  
Transfer-Path-Based Hardware-Reuse Strong PUF Achieving Modeling Attack Resilience With >200 Million Training CRPs Journal article
Xu, Chongyao, Zhang, Jieyun, Law, Man-Kay, Zhao, Xiaojin, Mak, Pui-In, Martins, Rui P.. Transfer-Path-Based Hardware-Reuse Strong PUF Achieving Modeling Attack Resilience With >200 Million Training CRPs[J]. IEEE Transactions on Information Forensics and Security, 2023, 18, 2188 - 2203.
Authors:  Xu, Chongyao;  Zhang, Jieyun;  Law, Man-Kay;  Zhao, Xiaojin;  Mak, Pui-In; et al.
Favorite | TC[WOS]:4 TC[Scopus]:6  IF:6.3/7.3 | Submit date：2023/03/29
Field-programmable Gate Array (Fpga)  Hardware Reuse  Machine Learning (Ml) Attack  Multiplier  Physical Unclonable Function (Puf)  Response Stream (Rs)  Transfer Path (Tp)  
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF Journal article
Qirui Ren, Qiang Huo, Zhisheng Chen, Qi Gao, Yiming Wang, Yiming Yang, Hao Wu, Xiangqu Fu, Xiaoxin Xu, Qing Luo, Jianfeng Gao, Chengying Chen, Xiaojin Zhao, Dengyun Lei, Xinghua Wang, Feng Zhang, Yong Chen, Pui-In Mak. A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 31(2), 243-252.
Authors:  Qirui Ren;  Qiang Huo;  Zhisheng Chen;  Qi Gao;  Yiming Wang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:2.8/2.8 | Submit date：2023/01/30
Current Sense Amplifier (Csa)  Low Cost  Low Power  Physical Unclonable Function (Puf)  Radio Frequency Identification Technology (Rfid)  Resistive Ram (rRam)  Security  
A 4T/Cell Amplifier-Chain-Based XOR PUF with Strong Machine Learning Attack Resilience Journal article
Zhang, Jieyun, Xu, Chongyao, Law, Man Kay, Jiang, Yang, Zhao, Xiaojin, Mak, Pui In, Martins, Rui P.. A 4T/Cell Amplifier-Chain-Based XOR PUF with Strong Machine Learning Attack Resilience[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(1), 366-377.
Authors:  Zhang, Jieyun;  Xu, Chongyao;  Law, Man Kay;  Jiang, Yang;  Zhao, Xiaojin; et al.
Favorite | TC[WOS]:17 TC[Scopus]:18  IF:5.2/4.5 | Submit date：2022/02/21
Amplifier Chain  Hardware Security  Machine Learning Attack  Physical Unclonable Function (Puf)  
Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections with <0.83% Bit-Error Rate Conference paper
Xu, Chongyao, Zhang, Jieyun, Law, Man-Kay, Jiang, Yang, Zhao, Xiaojin, Mak, Pui-ln, Martins, Rui P.. Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections with <0.83% Bit-Error Rate[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021.
Authors:  Xu, Chongyao;  Zhang, Jieyun;  Law, Man-Kay;  Jiang, Yang;  Zhao, Xiaojin; et al.
Favorite | TC[WOS]:4 TC[Scopus]:5 | Submit date：2022/08/21
A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise Journal article
Zhao,Qiang, Zheng,Wenhan, Zhao,Xiaojin, Cao,Yuan, Zhang,Feng, Law,Man Kay. A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67(11), 3866-3879.
Authors:  Zhao,Qiang;  Zheng,Wenhan;  Zhao,Xiaojin;  Cao,Yuan;  Zhang,Feng; et al.
Favorite | TC[WOS]:25 TC[Scopus]:26  IF:5.2/4.5 | Submit date：2021/03/11
Dynamic Entropy Source  Full Reconfigurability  High Reliability  Physical Unclonable Function  Resistive Random Access Memory  True Random Number Generator  
An N × N Multiplier-Based Multi-Bit Strong PUF Using Path Delay Extraction Conference paper
Chongyao Xu, Jieyun Zhang, Man-Kay Law, Xiaojin Zhao, Pui-In Mak, Rui P. Martins. An N × N Multiplier-Based Multi-Bit Strong PUF Using Path Delay Extraction[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2020, 9180584.
Authors:  Chongyao Xu;  Jieyun Zhang;  Man-Kay Law;  Xiaojin Zhao;  Pui-In Mak; et al.
Favorite | TC[WOS]:1 TC[Scopus]:5 | Submit date：2022/01/25
Multiplier  Multi-bit  Physical Unclonable Function  Path Delay Extraction  
A 6.4pJ/Bit Strong Physical Unclonable Function Based on Multiple-Stage Amplifier Chain Conference paper
Jieyun Zhang, Xiaojin Zhao, Man-Kay Law, Chongyao Xu, Jiahao Liu, Pui-In Mak, Rui P. Martins. A 6.4pJ/Bit Strong Physical Unclonable Function Based on Multiple-Stage Amplifier Chain[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2020, 9180597.
Authors:  Jieyun Zhang;  Xiaojin Zhao;  Man-Kay Law;  Chongyao Xu;  Jiahao Liu; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2022/01/25
Energy Efficiency  Multi-stage Amplifier  Physical Unclonable Function  
A 4-μm diameter SPAD using less-doped N-Well guard ring in baseline 65-nm CMOS Journal article
Lu,Xin, Law,Man Kay, Jiang,Yang, Zhao,Xiaojin, Mak,Pui In, Martins,Rui P.. A 4-μm diameter SPAD using less-doped N-Well guard ring in baseline 65-nm CMOS[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67(5), 2223-2225.
Authors:  Lu,Xin;  Law,Man Kay;  Jiang,Yang;  Zhao,Xiaojin;  Mak,Pui In; et al.
Favorite | TC[WOS]:14 TC[Scopus]:16  IF:2.9/2.9 | Submit date：2021/03/04
Baseline Cmos  Premature Lateral Breakdown  Single-photon Avalanche Diode (Spad)  Small Pitch