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A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur Conference paper
Chen, Tianle, Ren, Hongyu, Yang, Zunsong, Huang, Yunbo, Meng, Xianghe, Yan, Weiwei, Zhang, Weidong, Zheng, Xuqiang, Guo, Xuan, Iizuka, Tetsuya, Mak, Pui In, Chen, Yong, Li, Bo. A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter and -76.5-dBc Reference Spur[C]:Institute of Electrical and Electronics Engineers Inc., 2024.
Authors:  Chen, Tianle;  Ren, Hongyu;  Yang, Zunsong;  Huang, Yunbo;  Meng, Xianghe; et al.
Favorite | TC[Scopus]:0 | Submit date：2024/10/10
A 1.4-Vppd64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS Conference paper
Cai, Chen, Zheng, Xuqiang, Chen, Yong, Wu, Danyu, Luan, Jian, Zhou, Lei, Wu, Jin, Liu, Xinyu. A 1.4-Vppd64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS[C], 2021, 527-530.
Authors:  Cai, Chen;  Zheng, Xuqiang;  Chen, Yong;  Wu, Danyu;  Luan, Jian; et al.
Favorite | TC[WOS]:7 TC[Scopus]:10 | Submit date：2021/12/08
A 1.55-to-32-gb/s four-lane transmitter with 3-tap feed forward equalizer and shared pll in 28-nm cmos Journal article
Cai, Chen, Zheng, Xuqiang, Chen, Yong, Wu, Danyu, Luan, Jian, Lu, Dechao, Zhou, Lei, Wu, Jin, Liu, Xinyu. A 1.55-to-32-gb/s four-lane transmitter with 3-tap feed forward equalizer and shared pll in 28-nm cmos[J]. Electronics (Switzerland), 2021, 10(16), 1873.
Authors:  Cai, Chen;  Zheng, Xuqiang;  Chen, Yong;  Wu, Danyu;  Luan, Jian; et al.
Favorite | TC[WOS]:3 TC[Scopus]:4  IF:2.6/2.6 | Submit date：2021/10/28
Cmos  Feed-forward Equalizer (Ffe)  High-speed Serial Interface  Phase-locked Loop (Pll)  Transmitter (Tx)  Voltage-controlled Oscillator (Vco)  
A 0.01-mm21.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase Conference paper
Zhao, Xiaoteng, Chen, Yong, Zheng, Xuqiang, Mak, Pui In, Martins, Rui P.. A 0.01-mm21.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase[C], 2021, 386-389.
Authors:  Zhao, Xiaoteng;  Chen, Yong;  Zheng, Xuqiang;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:6 TC[Scopus]:4 | Submit date：2021/12/08
Bang-bang Clock And Data Recovery (Bbcdr)  Clock Selection  Cmos  Frequency Acquisition  Frequency Detector (Fd)  Reference (Ref)  Ring Oscillator (Ro)  Strobe Point (Sp)