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A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing Journal article
Guo Mingqiang, Qi Liang, Zhao Weibing, Xiao Gangjun, Rui P. Martins, Sin Sai-Weng. A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4767-4780.
Authors:  Guo Mingqiang;  Qi Liang;  Zhao Weibing;  Xiao Gangjun;  Rui P. Martins; et al.
Adobe PDF | Favorite | TC[WOS]:1 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2023/08/21
Analog-to-digital Converter (Adc)  Successive Approximation Register (Sar)  Power-delay-optimized  Unbalanced N/p-mos Sizing Buffers  Monotonic Switching  
LSB-Reused Protection Technique in Secure SAR ADC against Power Side-Channel Attack Conference paper
Lele Fang, Jiahao Liu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins. LSB-Reused Protection Technique in Secure SAR ADC against Power Side-Channel Attack[C], 2022.
Authors:  Lele Fang;  Jiahao Liu;  Yan Zhu;  Chi-Hang Chan;  Rui Paulo Martins
Favorite | TC[WOS]:1 TC[Scopus]:2 | Submit date：2023/03/06
Convolution Neural Network (Cnn)  Lsb-reused  Power Side-channel Attack (Psa)  Successive Approximation Register Analog-to-digital Converter (Sar Adc)  Synchronous  
A low dropout regulator with PSR under-48dB up to 20GHz for a SARADC reference buffer Conference paper
Yi Zeng, Chi-Hang Chan, Yan Zhu, Rui P. Martins. A low dropout regulator with PSR under-48dB up to 20GHz for a SARADC reference buffer[C], 2022.
Authors:  Yi Zeng;  Chi-Hang Chan;  Yan Zhu;  Rui P. Martins
Favorite | TC[WOS]:0 TC[Scopus]:0 | Submit date：2023/03/06
Low Dropout Regulator (Ldo)  High Power Supply Rejection (Psr)  Reference Buffer  Successive-approximation-register (Sar)  Analog-to-digital Converter (Adc)  
LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter with Ripple Calibration Journal article
Wang,Hanyu, Sin,Sai Weng, Lam,Chi Seng, Maloberti,Franco, Martins,Rui Paulo. LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter with Ripple Calibration[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67(12), 4174-4186.
Authors:  Wang,Hanyu;  Sin,Sai Weng;  Lam,Chi Seng;  Maloberti,Franco;  Martins,Rui Paulo
Favorite | TC[WOS]:6 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2021/03/04
Power Management  Switching-mode Power Converters  Boost Dc-dc Converters  Analog-to-digital Converters (Adcs)  Pipelined Adc  Ripple Calibration  
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation Conference paper
Zheng, Z., Wei, W., Lagos, J., Martens, E., Zhu, Y., Chan, C. H., Craninckx, J., Martins, R. P.. 16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation[C], 2020.
Authors:  Zheng, Z.;  Wei, W.;  Lagos, J.;  Martens, E.;  Zhu, Y.; et al.
Favorite |  | Submit date：2022/01/25
Amplifiers  Analogue-digital Conversion  Calibration  Interpolation  Dynamic Pipelined Adc  Dynamic Pipelined Architecture  Linearized Dynamic Amplifier  Post-amplification Residue Generation Scheme  Residue Amplification  Complex Residue-transferring Realization  Residue Amplifier  Power Consumption  Sar Adc  Calibration Complexity  Aggressive Interpolation Factor  Flash Adc  Mm-wave 5g Receivers  Adc-based Serial Links  Power 5.5 Mw  Calibration  Quantization (Signal)  Clocks  System-on-chip  Interpolation  Prototype  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques Journal article
Zhang,Minglei, Chan,Chi Hang, Zhu,Yan, Martins,Rui P.. A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques[J]. IEEE Journal of Solid-State Circuits, 2019, 54(12), 3396-3409.
Authors:  Zhang,Minglei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:27 TC[Scopus]:41  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Low Power Supply  Process  Voltage  And Temperature (Pvt) Robustness  Successive Approximation Register (Sar)  Threshold Crossing Detector  Time Residue Generator (Trg)  Time-domain Adc  Time-to-digital Converter (Tdc)  Two-step Tdc  Voltage-to-time Converter (Vtc)  
A 4-b 7µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation Journal article
Lei, X.W., Zhu, Y., Chan, C. H., Martins, R. P.. A 4-b 7µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS,, 2019, 3365-3372.
Authors:  Lei, X.W.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
Bluetooth low energy (BLE)  frequency-shift keying (FSK)  low power  phase ADC.  
A 4-b 7-μ W phase domain ADC with time domain reference generation for low-power FSK/PSK Demodulation Journal article
Lei,Xuewei, Chan,Chi Hang, Zhu,Yan, Martins,Rui Paulo. A 4-b 7-μ W phase domain ADC with time domain reference generation for low-power FSK/PSK Demodulation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(9), 3365-3372.
Authors:  Lei,Xuewei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui Paulo
Favorite | TC[WOS]:0 TC[Scopus]:1  IF:5.2/4.5 | Submit date：2021/03/09
Bluetooth Low Energy (Ble)  Frequency-shift Keying (Fsk)  Low Power  Phase Adc  
A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle Operation for Medical Imaging Applications Journal article
Sunny S., Chen Y., Boon C.C.. A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle Operation for Medical Imaging Applications[J]. IEEE Sensors Journal, 2018, 18(11), 4553-4560.
Authors:  Sunny S.;  Chen Y.;  Boon C.C.
Favorite | TC[WOS]:18 TC[Scopus]:21  IF:4.3/4.2 | Submit date：2019/02/14
1.5-bit/cycle  Adc  Capacitive Digital-to-analog Converter (Cdac)  Cmos  Error Correction  Low Power  Medical Imaging  Redundancy  Sar  Successive Approximation Register