UM

Browse/Search Results:  1-4 of 4 Help

Selected(0)Clear Items/Page:    Sort:
A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection Journal article
Ren, Qirui, Chen, Chengying, Dong, Danian, Xu, Xiaoxin, Chen, Yong, Zhang, Feng. A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection[J]. Sensors, 2022, 22(16), 6096.
Authors:  Ren, Qirui;  Chen, Chengying;  Dong, Danian;  Xu, Xiaoxin;  Chen, Yong; et al.
Favorite | TC[WOS]:4 TC[Scopus]:4  IF:3.4/3.7 | Submit date:2023/01/30
Analog Front-end (Afe)  Cmos  Eeg  Rram-based Lowpass Fir Filter  Signal Process  Ultra-low Power  
A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS Conference paper
Arya Balachandran, Yong Chen, Chirn Chye Boon. A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS[C]:IEEE, 2019, 221-224.
Authors:  Arya Balachandran;  Yong Chen;  Chirn Chye Boon
Favorite | TC[Scopus]:17 | Submit date:2021/10/28
Cmos  Analog Front-end (Afe)  Low Frequency Equalization (Lfeq)  Inductorless  Continuous-time Linear Equalizer (Ctle)  Inductorless  Channel Loss  Decision Feedback Equalization (Dfe)  Receiver  
Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering Book
U Seng Pan, Martins Rui Paulo, Epifanio da Franca Jose de Albuquerque. Design of Very High-Frequency Multirate Switched-Capacitor Circuits – Extending the Boundaries Of CMOS Analog Front-End Filtering[M]. US:Springer US, 2006, 250.
Authors:  U Seng Pan;  Martins Rui Paulo;  Epifanio da Franca Jose de Albuquerque
Favorite | TC[Scopus]:0 | Submit date:2019/02/26
Cmos  Cmos Analog Integrated Circuit  Filter  Front-end Filtering  Gain & Offset Compensation  High-frequency  Multirate Signal Processing  Secs  Switched-capacitor  The Kluwer International Series In engIneerIng And Computer  Timing-mismatch And Jitter  Calculus  Consumption  Integrated Circuit  
I/Q imbalance modeling of quadrature wireless transceiver analog front-ends in SIMULINK Conference paper
Pui-In Mak, Weng-Ieng Mok, Seng-Pan U, R.P. Martins. I/Q imbalance modeling of quadrature wireless transceiver analog front-ends in SIMULINK[C], 2003, 2371-2374.
Authors:  Pui-In Mak;  Weng-Ieng Mok;  Seng-Pan U;  R.P. Martins
Favorite | TC[WOS]:0 TC[Scopus]:3 | Submit date:2019/02/11
Analog Front-end  Analog-double Quadrature Sampling  I/q Imbalance  Image-rejection  Quadrature Transceiver