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Line-transient enhancement techniques for multi-path hybrid DC–DC converter with <1% output overshoot/undershoot Journal article
Huihua Li, Qiaobo Ma, Yang Jiang, Man-Kay Law, Pui-In Mak, Rui P. Martins. Line-transient enhancement techniques for multi-path hybrid DC–DC converter with <1% output overshoot/undershoot[J]. ELECTRONICS LETTERS, 2022, 58(25), 952-956.
Authors:  ; et al.
Favorite | TC[WOS]:2 TC[Scopus]:3  IF:0.7/0.9 | Submit date：2023/01/30
Dc–dc Power Convertors  Integrated Circuit Design  Mixed Analogue Digital Integrated Circuits  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss Journal article
Balachandran, Arya, Chen, Yong, Choi, Pilsoon, Boon, Chirn Chye. 0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss[J]. ELECTRONICS LETTERS, 2018, 54(2).
Authors:  Balachandran, Arya;  Chen, Yong;  Choi, Pilsoon;  Boon, Chirn Chye
Favorite | TC[WOS]:7 TC[Scopus]:10  IF:0.7/0.9 | Submit date：2018/10/30
Equalisers  Circuit Feedback  Analogue Circuits  Random Sequences  Binary Sequences  Cmos Analogue Integrated Circuits  Inductorless Analogue Equaliser  Low-frequency Equalisation Compensation  Lfeq  Low-frequency Channel Loss  Active Feedback Topology  Negative Capacitance Circuit  Data Jitter  Pseudorandom Binary Sequence  Cmos Technology  Loss 15 Db  Bit Rate 13 gBit  s  Size 65 Nm  Voltage 1  2 v  
A 0.137-mm2 9-GHz Hybrid Class-B/C QVCO with Output Buffering in 65-nm CMOS Journal article
Amin, T., Mak, P. I., Martins, R. P.. A 0.137-mm2 9-GHz Hybrid Class-B/C QVCO with Output Buffering in 65-nm CMOS[J]. IEEE Microwave and Wireless Components Letters, 2014, 716-718.
Authors:  Amin, T.;  Mak, P. I.;  Martins, R. P.
Favorite | TC[WOS]:4 TC[Scopus]:5  IF:2.9/3.0 | Submit date：2022/01/24
Cmos Analogue Integrated Circuits  Inductors  Microwave Integrated Circuits  
A 1.7mW 0.22mm2 2.4GHz ZigBee RX exploiting a current-reuse blixer + hybrid filter topology in 65nm CMOS Conference paper
Mak, P. I., Martins, R. P.. A 1.7mW 0.22mm2 2.4GHz ZigBee RX exploiting a current-reuse blixer + hybrid filter topology in 65nm CMOS[C], N/A:IEEE, 2013, 448-449.
Authors:  Mak, P. I.;  Martins, R. P.
Favorite |  | Submit date：2022/01/24
CMOS analogue integrated circuits  filters  mixers (circuits)  radio receivers  voltage-controlled oscillators