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A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer Journal article
Cao, Yuefeng, Zhang, Minglei, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2024.
Authors:  Cao, Yuefeng;  Zhang, Minglei;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2024/07/04
Analog-to-digital Converter (Adc)  Process, Supply Voltage, And Temperature (Pvt)-robust  Sturdy Ring Amplifier (sRingamp)  Time-domain Quantizer  Time-to-digital Converter (Tdc)  Voltage-to-time Converter (Vtc)  
A Fully-Integrated Flexible Dual-Ring Switched-Capacitor DC–DC Converter With Fractional VCRs and Parasitic Reduction Journal article
Jiang, Yifan, Lu, Yan, Jiang, Junmin. A Fully-Integrated Flexible Dual-Ring Switched-Capacitor DC–DC Converter With Fractional VCRs and Parasitic Reduction[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024.
Authors:  Jiang, Yifan;  Lu, Yan;  Jiang, Junmin
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/08/05
Converter Ring  Dc–dc Converter  Dual-ring  Fractional Vcrs  G-v2 Metric  Fully-integrated Voltage Regulator (Fivr)  Parasitic Reduction  Switched Capacitor (Sc) Converter  
A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS Journal article
Lu, Xin, Wu, Jiangchao, Wang, Zhao, Xiang, Yifei, Liu, Liyuan, Mak, Pui In, Martins, Rui P., Law, Man Kay. A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(8), 3635 - 3639.
Authors:  Lu, Xin;  Wu, Jiangchao;  Wang, Zhao;  Xiang, Yifei;  Liu, Liyuan; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.0/3.7 | Submit date：2024/05/16
Coarse-fine Conversion  Cyclic Time-to-digital Converter (Tdc)  Delays  Gated-ring Oscillator (Gro)  Generators  Image Edge Detection  Logic Gates  Phase Domain Reset  Ring Oscillators  Signal Resolution  Switches  
A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application Journal article
Kee, Yong Jack, Ramiah, Harikrishnan, Churchill, Kishore Kumar Pakkirisami, Chong, Gabriel, Mekhilef, Saad, Lai, Nai Shyan, Chen, Yong, Mak, Pui In, Martins, Rui P.. A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application[J]. IEEE Access, 2023, 11, 97641-97653.
Authors:  Kee, Yong Jack;  Ramiah, Harikrishnan;  Churchill, Kishore Kumar Pakkirisami;  Chong, Gabriel;  Mekhilef, Saad; et al.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:3.4/3.7 | Submit date：2024/02/22
Cmos  Dc-to-dc Converter  Low Power Energy Harvesting  Power Conversion Efficiency (Pce)  Reconfigurable Charge Pump (Cp)  Ring-voltage Controlled Oscillator (Rvco)  
A Dual-Ring Switched-Capacitor DC-DC Converter With Systematic Fractional Conversion Ratios Conference paper
Yifan Jiang, Junmin Jiang, Yan Lu. A Dual-Ring Switched-Capacitor DC-DC Converter With Systematic Fractional Conversion Ratios[C]:Institute of Electrical and Electronics Engineers Inc., 2023.
Authors:  Yifan Jiang;  Junmin Jiang;  Yan Lu
Favorite | TC[WOS]:1 TC[Scopus]:2 | Submit date：2023/08/28
Converter-ring  Dc-dc  Dual-ring  Switched-capacitor Power Converter  Fractional Ratios  Charge Redistribution  
A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS Journal article
Zhang,Chenghao, Wei,Jiangbo, Chen,Yong, Liu,Maliang, Yang,Yintang. A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2023, 58(11), 3179-3193.
Authors:  Zhang,Chenghao;  Wei,Jiangbo;  Chen,Yong;  Liu,Maliang;  Yang,Yintang
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Calibration  Cmos  Folding  Gated Ring Oscillator (Gro)  Interpolation  Pulse Generator (Pg)  Time Domain (Td)  Voltage Domain (Vd)  
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation Journal article
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhou, Xionghui, Han, Mei, Stefano, Crovetti Paolo, Mak, Pui In, Martins, Rui P.. A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation[J]. International Journal of Circuit Theory and Applications, 2023, 51(5), 1988-2015.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhou, Xionghui;  Han, Mei; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:1.8/1.7 | Submit date：2023/06/05
Bang-bang Clock And Data Recovery (Bbcdr)  Current Mismatch  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Phase Interpolator (Pi)  R-2r Digital-to-analog Converter (Dac)  Ring Oscillator (Ro)  Switched-capacitor (Sc) Array  Wide Capture Range  
A 0.12-mm2 1.2-to-2.4 mW 1.3-to-2.65 GHz Fractional-N Bang-Bang Digital PLL with 8-μs Settling Time for Multi-ISM-Band ULP Radios Journal article
Un, K. F., Qi, G., Yin, J., Yang, S., Yu, S., Ieong, C. -I., Mak, P. I., Martins, R. P.. A 0.12-mm2 1.2-to-2.4 mW 1.3-to-2.65 GHz Fractional-N Bang-Bang Digital PLL with 8-μs Settling Time for Multi-ISM-Band ULP Radios[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 3307-3316.
Authors:  Un, K. F.;  Qi, G.;  Yin, J.;  Yang, S.;  Yu, S.; et al.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
digital phase-locked loop (DPLL)  bang-bang  digital-to-time converter (DTC)  gain calibration  voltage-controlled oscillator (VCO)  ring VCO  ultra-low-power (ULP)  ultra-fast settling  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
Un,Ka Fai, Qi,Gengzhen, Yin,Jun, Yang,Shiheng, Yu,Shupeng, Ieong,Chio In, Mak,Pui In, Martins,Rui P.. A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(9), 3307-3316.
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng; et al.
Favorite | TC[WOS]:11 TC[Scopus]:12  IF:5.2/4.5 | Submit date：2021/03/09
Bang-bang  Digital Phase-locked Loop (Dpll)  Digital-to-time Converter (Dtc)  Gain Calibration  Ring Vco  Ultra-fast Settling  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)  
Design Considerations of Distributed and Centralized Switched-Capacitor Converters for Power Supply On-Chip Journal article
Lu, Yan, Jiang, Junmin, Ki, Wing-Hung. Design Considerations of Distributed and Centralized Switched-Capacitor Converters for Power Supply On-Chip[J]. IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, 2018, 6(2), 515-525.
Authors:  Lu, Yan;  Jiang, Junmin;  Ki, Wing-Hung
Favorite | TC[WOS]:17 TC[Scopus]:19  IF:4.6/5.3 | Submit date：2018/10/30
Active-matrix Light-emitting Diode (Amled)  Amplifier  Charge Pump  Converter Ring  Dc-dc Converter  Digital Control  Dynamic Voltage Scaling (Dvs)  Fully Integrated Voltage Regulator (Fivr)  Hybrid Converter  Low-dropout Regulator (Ldo)  Multilevel  Multiphase  Resonant Converter  Switched-capacitor (Sc) Power Converter  Voltage-controlled Oscillator (Vco)