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Optimal Design of RDARS-aided Multi-user Systems with Low-resolution DACs Conference paper
Wang, Jintao, Ma, Chengzhi, Ma, Shaodan. Optimal Design of RDARS-aided Multi-user Systems with Low-resolution DACs[C]:Institute of Electrical and Electronics Engineers Inc., 2024, 536-540.
Authors:  Wang, Jintao;  Ma, Chengzhi;  Ma, Shaodan
Favorite | TC[Scopus]:0 | Submit date：2024/11/05
Wireless Communication  Heuristic Algorithms  Transmitting Antennas  Signal Processing Algorithms  Benchmark Testing  Reflector Antennas  Downlink  Hardware  Surface Treatment  Antenna Arrays  Distributed Antenna System  Low-resolution Dac  Reconfigurable Intelligent Surface  Block Coordinate Descent  
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique Journal article
Wang,Lin, Chen,Yong, Yang,Chaowei, Zhao,Xiaoteng, Mak,Pui In, Maloberti,Franco, Martins,Rui P.. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(7), 2637-2650.
Authors:  Wang,Lin;  Chen,Yong;  Yang,Chaowei;  Zhao,Xiaoteng;  Mak,Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4  IF:5.2/4.5 | Submit date：2023/08/03
Bang-bang Clock And Data Recovery (Bbcdr)  Wide Capture Range  Single Loop  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Deliberate Current Mismatch  Ring Oscillator (Ro)  R-2r Dac  Positive (Pnc)  Negative (Nnc) And Zero (Znc) Net Current  Cmos  Bang-bang Phase Detector (Bbpd)  
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation Journal article
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhou, Xionghui, Han, Mei, Stefano, Crovetti Paolo, Mak, Pui In, Martins, Rui P.. A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation[J]. International Journal of Circuit Theory and Applications, 2023, 51(5), 1988-2015.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhou, Xionghui;  Han, Mei; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:1.8/1.7 | Submit date：2023/06/05
Bang-bang Clock And Data Recovery (Bbcdr)  Current Mismatch  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Phase Interpolator (Pi)  R-2r Digital-to-analog Converter (Dac)  Ring Oscillator (Ro)  Switched-capacitor (Sc) Array  Wide Capture Range  
A 880 nW, 100 kS/s, 13 bit Differential Relaxation-DAC in 180 nm Conference paper
Rubino,Roberto, Musolino,Francesco, Chen,Yong, Richelli,Anna, Crovetti,Paolo. A 880 nW, 100 kS/s, 13 bit Differential Relaxation-DAC in 180 nm[C]. Bosch, et al., Huawei, Photeon Technologies, Synopsys:Institute of Electrical and Electronics Engineers Inc., 2023, 269-272.
Authors:  Rubino,Roberto;  Musolino,Francesco;  Chen,Yong;  Richelli,Anna;  Crovetti,Paolo
Favorite | TC[WOS]:3 TC[Scopus]:3 | Submit date：2023/08/03
Consumer Data Converter.  D/a Converter (Dac)  Digital Intensive  Relaxation D/a Converter (Redac)  Ultra-low Area  Ultra-low Power  
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR Journal article
Liao, Qiwen, Zhang, Yuguang, Ma, Siyuan, Wang, Lei, Li, Leliang, Li, Guike, Zhang, Zhao, Liu, Jian, Wu, Nanjian, Liu, Liyuan, Chen, Yong, Xiao, Xi, Qi, Nan. A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR[J]. IEEE Journal of Solid-State Circuits, 2022, 57(3), 767-780.
Authors:  Liao, Qiwen;  Zhang, Yuguang;  Ma, Siyuan;  Wang, Lei;  Li, Leliang; et al.
Favorite | TC[WOS]:24 TC[Scopus]:30  IF:4.6/5.6 | Submit date：2022/03/28
Clock And Data Recovery (Cdr)  Cmos  Distributed Driver  Four-level Pulse Amplitude (Pam-4)  Machâ Zehnder Modulator (Mzm)  Optical Digital-to-analog Converter (Dac)  Silicon Photonic (Siph)  Transmitter (Tx)  
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme Conference paper
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhao, Xiaoteng, Mak, Pui In, Maloberti, Franco, Martins, Rui P.. A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2022.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhao, Xiaoteng;  Mak, Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1 | Submit date：2023/03/06
Hybrid Control Circuit (Hcc)  Deliberate Current Mismatch  Charge Pump (Cp)  Ring Oscillator (Ro)  R-2r Dac  Positive (Pnc)  Negative (Nnc)  Zero (Znc) Net Current  
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs Journal article
Jiang, D., Sin, S. W., Qi, L., Wang, G., Martins, R. P.. Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs[J]. IEEE Open Journal of the Solid-State Circuits Society, 2021, 129-139.
Authors:  Jiang, D.;  Sin, S. W.;  Qi, L.;  Wang, G.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
ADC  analog-to-digital converter  DAC  digital-to-analog-converter  hybrid ADC  incremental ADC (I-ADC)  delta-sigma modulator  time-Interleaving  extrapolating  noise shaping  successive approximation register  SAR.  
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation Journal article
Jiang, Dongyang, Qi, Liang, Sin, Sai Weng, Maloberti, Franco, Martins, Rui P.. A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56(8), 2375-2387.
Authors:  Jiang, Dongyang;  Qi, Liang;  Sin, Sai Weng;  Maloberti, Franco;  Martins, Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:14  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Converter (Adc)  Data Weighting Average (Dwa)  Delta-sigma Modulator (Dsm)  Digital Bank Filters  Digital-to-analog Converter (Dac)  Discrete-time (Dt)  Dithering  Dynamic Element Matching (Dem)  Extrapolation  Noise-coupling  Time-domain Analysis  Time-interleaved (Ti)  
A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array Journal article
Dong, Li, Song, Yan, Xie, Yi, Xin, Youze, Li, Ken, Jing, Xixin, Zhang, Bing, Gui, Xiaoyan, Geng, Li. A 10-bit 20-MS/s SAR DAC achieving 57.9-dB SNDR using insensitive geometry DAC array[J]. Microelectronics Journal, 2021, 113, 105109.
Authors:  Dong, Li;  Song, Yan;  Xie, Yi;  Xin, Youze;  Li, Ken; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.9/1.7 | Submit date：2021/12/08
Analog-to-digital Converter (Adc)  Area-efficient  Dac Mismatch  High Linearity  Insensitive Geometry  
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
Qi,Liang, Jain,Ankesh, Jiang,Dongyang, Sin,Sai Weng, Martins,Rui P., Ortmanns,Maurits. A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 344-355.
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.; et al.
Favorite | TC[WOS]:54 TC[Scopus]:48  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)