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A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS Journal article
Yang,Jian, Pan,Quan, Yin,Jun, Mak,Pui In. A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS[J]. IEEE Transactions on Microwave Theory and Techniques, 2023, 71(8), 3596 - 3604.
Authors:  Yang,Jian;  Pan,Quan;  Yin,Jun;  Mak,Pui In
Favorite | TC[WOS]:4 TC[Scopus]:4  IF:4.1/4.2 | Submit date：2023/08/03
Charge Pump (Cp)  Clock Generator  Delay-locked Loop (Dll)  Locking Range  Multiphase Clock  Phase Accuracy  
A process-and temperature-insensitive current-controlled delay generator for sampled-data systems Conference paper
Wei, H. G., Chio, U.F., Zhu, Y., U, S.P., Martins, R. P.. A process-and temperature-insensitive current-controlled delay generator for sampled-data systems[C], 2008.
Authors:  Wei, H. G.;  Chio, U.F.;  Zhu, Y.;  U, S.P.;  Martins, R. P.
Favorite |  | Submit date：2022/01/24
Process & temperature-insensitive  Delay generator  Current-controlled