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Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference Journal article
Yu Duan, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins. Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(12), 4799-4809.
Authors:  Yu Duan;  Chi-Hang Chan;  Yan Zhu;  Rui Paulo Martins
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2023/01/30
Digital-regulated Supply Noise Cancellation (Dsnc)  Interference Reduction  Jitter  Phase Noise Cancellation (Pnc)  Phase-locked Loop  Phase-locked Loop (Pll)  Ring Voltage-controlled Oscillator (Rvco)  Supply Noise Suppression  
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
Chen, Peng, Yin, Jun, Zhang, Feifei, Mak, Pui In, Martins, Rui P., Staszewski, Robert Bogdan. Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), 196-206.
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.; et al.
Favorite | TC[WOS]:5 TC[Scopus]:7  IF:5.2/4.5 | Submit date：2021/09/20
All-digital Pll (adPll)  Build-in Self-test (Bist)  Digital-to-time Converter (Dtc)  Fractional Spur  Jitter  Mismatch  Noise Shaping  Phase/frequency Detector (Pfd)  Phase Frequency Detectors  Self Calibration  Time-to-digital Converter (Tdc).  
A 600-µm2 Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui-In, Li, Qiang, Martins, Rui P.. A 600-µm2 Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108 - 3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui-In; et al.
Favorite | TC[WOS]:6 TC[Scopus]:7  IF:4.0/3.7 | Submit date：2022/01/25
Area  Analog Phase-locked Loop (Pll)  Cmos  Charge-sharing Integrator  Digital Pll  Hybrid Pll  Integrator  Integer-n  Jitter  Ring Oscillator  Ultra-low Power  
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui In, Li, Qiang, Martins, Rui P.. A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108-3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In; et al.
Favorite | TC[WOS]:6 TC[Scopus]:7  IF:4.0/3.7 | Submit date：2021/09/20
Analog Phase-locked Loop (Pll)  Area  Charge-sharing Integrator  Cmos  Digital Pll  Hybrid Pll  Integer-n  Integrator  Jitter  Ring Oscillator  Ultra-low Power  
A 600-µm2 Ring-VCO-Based Type-II Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui-In, Li, Qiang, Martins, Rui P.. A 600-µm2 Ring-VCO-Based Type-II Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108-3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui-In; et al.
Favorite | TC[WOS]:6 TC[Scopus]:7  IF:4.0/3.7 | Submit date：2022/08/19
Area  Analog Phase-locked Loop (Pll)  Cmos  Charge-sharing Integrator  Digital Pll  Hybrid Pll  Integrator  Integer-n  Jitter  Ring Oscillator  Ultra-low Power  
A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs Journal article
Yang, S., Yin, J., Mak, P. I., Martins, R. P.. A 0.0056-mm² -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 88-98.
Authors:  Yang, S.;  Yin, J.;  Mak, P. I.;  Martins, R. P.
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2022/01/24
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter  
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs Journal article
Shiheng Yang, Jun Yin, Pui-In Mak, Rui P. Martins. A 0.0056-mm2 -249-dB-FoM All-Digital MDLL using a block-sharing offset-free frequency-tracking loop and dual multiplexed-ring VCOs[J]. IEEE Journal of Solid-State Circuits, 2019, 54(1), 88-98.
Authors:  Shiheng Yang;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:27 TC[Scopus]:28  IF:4.6/5.6 | Submit date：2019/02/11
Clock Multiplier  Digital-controlled Delay Line (Dcdl)  Frequency-tracking Loop (Ftl)  Injection-locked Phase-locked Loop (Il-pll)  Multiplying Delay-locked Loop (Mdll)  Phase Noise  Ring Voltage-controlled Oscillator (Rvco)  Root-mean-square (Rms) Jitter