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A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator Journal article
Yue Hu, Yuekai Liu, Xinyu Qin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi. A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 1-13.
Authors:  Yue Hu;  Yuekai Liu;  Xinyu Qin;  Yan Liu;  Mingqiang Guo; et al.
Adobe PDF | Favorite | TC[WOS]:2 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2023/08/22
Continuous-time Delta-sigma Modulator (Dsm)  Time-interleaved (Ti)  Cascaded Integrator Of Distributed Feedforward (Ciff)  Excess Loop Delay (Eld) Compensation  
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
Qi,Liang, Jain,Ankesh, Jiang,Dongyang, Sin,Sai Weng, Martins,Rui P., Ortmanns,Maurits. A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 344-355.
Authors:  Qi,Liang;  Jain,Ankesh;  Jiang,Dongyang;  Sin,Sai Weng;  Martins,Rui P.; et al.
Favorite | TC[WOS]:54 TC[Scopus]:48  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)  
A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance Journal article
Qi, L., Jain, A., Jiang, D., Sin, S. W., Martins, R. P., Ortmanns, M.. A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance[J]. IEEE Journal of Solid-State Circuits, 2019, 55(2), 344-355.
Authors:  Qi, L.;  Jain, A.;  Jiang, D.;  Sin, S. W.;  Martins, R. P.; et al.
Favorite | TC[WOS]:54 TC[Scopus]:48  IF:4.6/5.6 | Submit date：2022/01/25
Analog-to-digital Converter (Adc)  Continuous Time (Ct)  Digital-to-analog Converter (Dac) Linearization  Excess Loop Delay (Eld) Compensation  Filter  Finite-impulse Response (Fir)  Multibit Quantization  Noise Coupling (Nc)  Sturdy Multistage Noise-shaping (Smash)  Successive-approximation Register (Sar)  
才能信号抑或薪酬辩护:超额薪酬与战略信息披露 Journal article
Cheng, X., Liu, J., Chen, J.J.. 才能信号抑或薪酬辩护:超额薪酬与战略信息披露[J]. 金融研究, 2015, 146-161.
Authors:  Cheng, X.;  Liu, J.;  Chen, J.J.
Favorite |  | Submit date：2022/08/22
Excess compensation  Information disclosure on strategy  Management talent signaling hypothesis  Justifying compensation hypothesis  
Excess-loop-delay compensation technique for CT Delta Sigma modulator with hybrid active-passive loop-filters Journal article
Cai, C.Y., Jiang, Y., Sin, S. W., U, S.P., Martins, R. P.. Excess-loop-delay compensation technique for CT Delta Sigma modulator with hybrid active-passive loop-filters[J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2013, 35-46.
Authors:  Cai, C.Y.;  Jiang, Y.;  Sin, S. W.;  U, S.P.;  Martins, R. P.
Favorite | TC[WOS]:1   IF:1.2/1.0 | Submit date：2022/01/24
Ct Delta Sigma Modulator  Hybrid Active-passive Loop-filter  Excess-loop-delay For Hybrid Active-passive Loop-filter  Excess-loop-delay Compensation Techniques For Hybrid Active-passive Loop-filter  
Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters Journal article
Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui P. Martins. Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters[J]. Analog Integrated Circuits and Signal Processing, 2013, 76(1), 35-46.
Authors:  Chen-Yan Cai;  Yang Jiang;  Sai-Weng Sin;  Seng-Pan U;  Rui P. Martins
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:1.2/1.0 | Submit date：2019/02/11
Ct Δς Modulator  Excess-loop-delay Compensation Techniques For Hybrid Active-passive Loop-filter  Excess-loop-delay For Hybrid Active-passive Loop-filter  Hybrid Active-passive Loop-filter